Siemens Deploys AI to Speed Chip Design

The use of agentic AI in Siemens' Questa One platform represents a significant shift from traditional electronic design automation (EDA). Unlike earlier AI that assisted with specific tasks, agentic AI can autonomously manage and optimize complex workflows, make decisions, and reason through the chip design and verification process. This is part of a broader industry trend where AI is becoming less of a tool and more of a collaborator for engineers. RTL (register-transfer level) sign-off is a critical and often time-consuming phase in chip development. It ensures the chip's design is structurally sound and ready for the subsequent manufacturing stages. Errors missed at this stage can lead to costly delays and failures later in the process. Siemens' AI-powered approach aims to tackle the growing verification productivity gap, a major challenge as chip designs become increasingly complex. The goal is to automate the generation of verification artifacts like testbenches and assertions, and to intelligently prioritize regression testing. Early adopters of similar AI-driven verification have reported slashing verification times from weeks to days. This move is part of a larger AI-centric strategy at Siemens EDA, which includes the Solido Simulation Suite. The Solido suite utilizes AI to dramatically speed up simulations for analog and mixed-signal chips, which are crucial for applications in automotive, wireless communication, and the Internet of Things (IoT). The broader vision for agentic AI in chip design involves raising the level of abstraction from RTL to natural language specifications. This would allow engineers to describe the desired functionality in plain language, with the AI handling the intricate details of the design and verification. Major players in the EDA space, including Synopsys, are also heavily investing in agentic AI, signaling a fundamental change in how semiconductors are designed.