CoWoS = next choke point
The advanced packaging tech many AI GPUs rely on — TSMC’s CoWoS — is being called the next industry bottleneck because NVIDIA has reserved more than half of available capacity through 2027, squeezing rivals who also need that packaging. That reservation dynamic is forcing companies to hunt for alternatives and is one reason TSMC says it will expand output aggressively, targeting about 130,000 wafers per month by late 2026 as it scales capacity. (x.com) (x.com)
The chip shortage story in artificial intelligence has moved one step down the assembly line. Nvidia has locked up most of Taiwan Semiconductor Manufacturing Company’s top-end advanced packaging capacity, and that packaging step is now being treated as the next constraint on how many AI systems can actually ship. (cnbc.com) Advanced packaging is the part where separate pieces of silicon get turned into one working product. A graphics chip, its high-bandwidth memory stacks, and the wiring that links them all have to be mounted, connected, protected, and tested before a server maker can install them in a rack. (cnbc.com) Taiwan Semiconductor Manufacturing Company’s version of that process is called chip-on-wafer-on-substrate. The company says this method lets one logic chip sit beside multiple memory stacks on a silicon bridge called an interposer, and it supports packages larger than twice a normal reticle size, or about 1,700 square millimeters. (tsmc.com) That design became central to modern AI chips because high-bandwidth memory has to sit physically close to the processor to move data fast enough. Taiwan Semiconductor Manufacturing Company says chip-on-wafer-on-substrate is built for high-performance computing and can integrate more than four high-bandwidth memory stacks in one package. (tsmc.com) The squeeze started before this week’s headlines. TrendForce said in April 2024 that Nvidia’s demand alone was expected to consume more than half of Taiwan Semiconductor Manufacturing Company’s chip-on-wafer-on-substrate capacity in 2025 as Blackwell systems ramped. (trendforce.com) Now that reservation pattern is colliding with a wider customer list. CNBC reported on April 8 that Nvidia has reserved the majority of the most advanced packaging capacity available at Taiwan Semiconductor Manufacturing Company, while rivals and custom chip programs are all chasing the same assembly step. (cnbc.com) That is why companies that do not buy Nvidia chips are suddenly talking about packaging vendors, not just chip designers. If the factory can etch the silicon but cannot package the finished processor with memory, the chip is like a car engine with no transmission. (cnbc.com) Taiwan Semiconductor Manufacturing Company has been racing to add capacity for two years. TrendForce said in May 2024 that the company planned to grow chip-on-wafer-on-substrate output at more than a 60% compound annual rate through 2026, which would more than quadruple capacity from 2023 levels. (trendforce.com) The target has since gotten even bigger. Industry estimates compiled by TrendForce say Taiwan Semiconductor Manufacturing Company is aiming for roughly 120,000 to 130,000 chip-on-wafer-on-substrate wafers per month by the end of 2026, up from about 75,000 to 80,000 today. (trendforce.com) The bottleneck is also pushing work outside Taiwan Semiconductor Manufacturing Company. CNBC reported that Intel is pitching its own advanced packaging to outside customers including Amazon and Cisco, and Elon Musk has committed packaging work for SpaceX, xAI, and Tesla to Intel’s planned Texas facility. (cnbc.com) So the fight over artificial intelligence hardware is no longer just about who can design the best chip or book the most wafer starts. It is also about who can secure the last, fussy, high-precision step that turns a pile of expensive silicon and memory into one finished accelerator. (cnbc.com)
