AMD ramps Venice on TSMC 2nm

AMD said on May 21 that its next-generation EPYC server processor, codenamed Venice, is ramping production in Taiwan on TSMC's 2nm process technology, with future plans to ramp production at TSMC's Arizona fabrication site. The announcement gives AMD a new manufacturing milestone for the chipmaker's sixth-generation EPYC line and ties that product directly to TSMC's N2 node. AMD also said Venice is the first high-performance computing product in the industry to reach production ramp on TSMC's advanced 2nm process. (amd.com) (tsmc.com) The statement adds a new step in a program AMD had previewed in April 2025, when it said Venice had been taped out and brought up on TSMC's 2nm technology. That earlier disclosure established Venice as AMD's first announced EPYC design on N2; the new release moves the chip from silicon milestone to production ramp. ### What, exactly, did AMD announce about Venice? AMD said Venice is now ramping production in Taiwan, not merely in design or early silicon validation. (amd.com) The company described Venice as its next-generation EPYC processor and identified it as the sixth-generation EPYC CPU. The May 21 release did not provide a launch date, shipment date or customer availability window. That matters because a production-ramp announcement confirms manufacturing progress, but it does not by itself show when cloud providers, OEMs or enterprise buyers will be able to deploy systems in volume. (amd.com) That inference is based on the absence of timing detail in AMD's release and on TSMC's own node roadmap. ### Why does the 2nm piece matter here? TSMC says its N2 technology is part of its 2nm family and that volume production for N2P, an extension of that family, is scheduled for the second half of 2026. (amd.com) AMD's announcement places Venice on that manufacturing path and links its next EPYC generation to TSMC's latest leading-edge node. AMD had already said in 2025 that Venice was the first HPC product to be taped out and brought up on TSMC N2. On May 21, AMD used similar language again, this time saying Venice is the first HPC product in the industry to achieve production ramp on TSMC's advanced 2nm technology. (amd.com) ### What does the Arizona reference add? AMD said future production of Venice is planned for TSMC's Arizona fabrication facility. TSMC says it began its Arizona project with a $12 billion plan announced in May 2020 and later expanded that commitment in December 2022 with a second fab, bringing total investment to $40 billion. (tsmc.com) The Arizona reference does not mean Venice will be available from that site immediately. AMD's wording was "future plans" to ramp production there, and the company did not give a date, fab identifier or output target. (amd.com) ### Where does this fit in AMD's broader roadmap? AMD said in the same May 21 announcement that it is continuing 2nm product expansion with Verano, which it described as a follow-on to Venice using LPDDR integration. That places Venice as the first named EPYC step in AMD's 2nm server roadmap rather than a one-off manufacturing test vehicle. (amd.com) TSMC's 2026 symposium materials also show the foundry continuing to market advances from transistor scaling to system integration, underscoring the broader ecosystem event around which these disclosures were made. (amd.com) ### What should readers not assume from this announcement? AMD did not say Venice revenue would begin this quarter, and it did not identify customers, server makers or deployment dates. For buyers and investors, the missing fields are product availability, qualification timing and customer adoption schedules. (amd.com) That is an inference from what AMD disclosed and did not disclose, rather than a statement by the company. TSMC's published roadmap points to continued 2nm-family production milestones through 2026, while AMD's next public markers are likely to be product launch details, customer system announcements or a dated Arizona ramp update. (tsmc.com) AMD's press-release archive lists the Venice production-ramp announcement on May 20, 2026, and TSMC's events page shows additional 2026 symposium dates later this year. (amd.com 1) (amd.com 2)