TSMC's 2029 roadmap

TSMC used its North America Technology Symposium on April 22 to lay out a chipmaking roadmap through 2029, with a new A13 process scheduled for production that year. (businesswire.com) Chipmaking nodes are the manufacturing steps that pack more transistors into the same space, usually to raise speed or cut power use. TSMC said A13 is a direct shrink of A14, with 6% area savings, backward-compatible design rules, and production planned for 2029. (businesswire.com) TSMC also previewed A12, an A14-based variant with backside power delivery called Super Power Rail, and said that process is also due in 2029. The company introduced N2U as another 2-nanometer-family option for 2028, with 3% to 4% higher speed or 8% to 10% lower power than N2P and a 1.02x to 1.03x logic-density gain. (businesswire.com) The schedule marks a change from last year’s roadmap. In April 2025, TSMC said A14 would enter production in 2028 and described A16 as a 2026-production technology; Tom’s Hardware reported this week that A16 has now slipped to 2027 in TSMC’s updated roadmap. (businesswire.com) (tomshardware.com) That matters because TSMC’s biggest customers, including makers of artificial-intelligence accelerators and smartphone processors, plan products years ahead and match designs to specific manufacturing windows. TSMC said the 2026 symposium carried the theme “Expanding AI with Leadership Silicon,” and its 2025 event tied A14 and advanced packaging directly to AI demand. (businesswire.com 1) (businesswire.com 2) Another part of the update is what TSMC did not put on the near-term roadmap: High-Numerical-Aperture extreme ultraviolet lithography, the next generation of the light-based patterning tools used to print chip features. Overclock3D reported that TSMC plans to keep using today’s low-NA EUV tools through at least 2029 rather than move to High-NA on these nodes. (overclock3d.net) TSMC has not abandoned next-generation lithography research altogether. Its future R&D page still lists “next-generation EUV lithography and related patterning technology” as an active research area, alongside work on nodes beyond A14, 3D transistors, new memories, and lower-resistance interconnects. (tsmc.com) The near-term emphasis instead stays on refining existing transistor designs and combining them with packaging that links multiple chips together in one system. At the 2025 symposium, TSMC said its 9.5-reticle CoWoS packaging would reach volume production in 2027 and that SoW-X, a wafer-sized system, was also set for 2027. (businesswire.com) So the 2029 roadmap is less about one dramatic tool change than about extending TSMC’s current playbook: smaller logic nodes, backside power delivery, and bigger multi-chip packages. For customers building the next wave of AI and mobile chips, the message from Santa Clara was a longer runway built on familiar manufacturing methods. (businesswire.com) (overclock3d.net)