TSMC shifts bottleneck to packaging
- TSMC announced plans to open an advanced chip‑packaging plant in Arizona by 2029, moving packaging closer to US customers. - The foundry also signalled cost discipline, delaying use of ASML’s High‑NA EUV and publishing a roadmap through 2029 including A13 and A16 timing changes. - The message: leading‑node access alone isn’t enough; packaging and economics now shape silicon availability and product roadmaps (reuters.com, bloomberg.com, tomshardware.com)
TSMC said it plans to add advanced chip packaging in Arizona by 2029, extending its U.S. buildout beyond wafer fabrication. (reuters.com) Packaging is the step that connects finished silicon to memory and other chips, turning separate pieces into one working module for servers, phones, and accelerators. TSMC executive Kevin Zhang said in Santa Clara on April 22 that the company aims to have the Arizona packaging site ready by 2029. (reuters.com) TSMC’s Arizona plan already spans six wafer fabs, two advanced packaging facilities and a research-and-development team center, according to the company’s U.S. site. In March 2025, TSMC said it would raise total U.S. investment to $165 billion. (tsmc.com, tsmc.com) The timing reflects where demand has piled up. Artificial-intelligence chips increasingly rely on advanced packaging such as Chip-on-Wafer-on-Substrate, or CoWoS, to place logic and high-bandwidth memory side by side inside one package. (tsmc.com, tsmc.com) TSMC used the same symposium to show more caution on manufacturing costs. Bloomberg reported the company has no current plan to use ASML’s High-NA extreme ultraviolet tools through 2029 because the machines cost more than 350 million euros, or about $410 million, each. (bloomberg.com) The roadmap shifted too. TSMC said A13 is set for production in 2029, while Tom’s Hardware reported A16 has slipped to 2027 as the company split its leading-edge plans between client chips and higher-power data-center designs. (tsmc.com, tomshardware.com) That leaves customers with two separate constraints: access to the newest transistor node and access to enough packaging capacity to assemble large AI processors. Reuters reported the Arizona packaging move is meant to put that assembly step closer to U.S. customers. (reuters.com) TSMC and Amkor had already signed a memorandum in October 2024 to work on advanced packaging and test in Arizona, tying foundry output to local back-end assembly. The new 2029 target suggests TSMC now wants more of that bottleneck addressed inside its own Arizona footprint. (tsmc.com, reuters.com) TSMC’s message on April 22 was less about a single node than about the full path from wafer to finished module. By 2029, in TSMC’s plan, more of that path will sit in Arizona — and more of the schedule will depend on packaging economics as much as lithography. (reuters.com, bloomberg.com, tsmc.com)
