Foundry capacity pressure
Analysts flagged rising TPU and custom‑silicon demand as competing for advanced‑node foundry capacity, potentially squeezing access to high‑end chips like GPUs. The crowding at fabs is already altering vendor roadmaps and supply expectations. (tickerreport.com)
SemiAnalysis projects AI accelerators will consume about 86% of TSMC’s N3 capacity by 2027, a shift that concentrates wafer demand on a single advanced node. (the-decoder.com) Independent channel checks show lead times for 3nm wafers and associated accelerators have stretched beyond 50 weeks, with 3nm capacity effectively fully allocated into late 2027. (siliconanalysts.com) TSMC Chairman‑CEO C.C. Wei told the SIA awards in November 2025 that the company’s advanced‑node capacity is “around 3‑times short” of what major customers plan to consume. (tomshardware.com) Industry reporting lists nearly every major 2026 data‑center accelerator moving to N3 — Nvidia’s Rubin, Google’s TPU v7/v8, Amazon’s Trainium3 and AMD’s MI350X — creating a simultaneous ramp demand shock. (the-decoder.com) Advanced packaging is an additional choke point: CoWoS packaging demand outstrips supply by an estimated 40–50%, and HBM3e memory supply is tightly constrained with prices forecast to rise roughly 15–20%. (siliconanalysts.com) SemiAnalysis and other analysts calculate that reallocating about 25% of smartphone N3 wafer starts could yield roughly 700,000 extra Rubin GPUs or 1.5 million TPU v7 units, illustrating the scale of tradeoffs between mobile and AI customers. (the-decoder.com) TSMC has accelerated capex and fab construction plans, but multiple analyst groups warn those builds won’t close the shortage for at least two years, leaving packaging, HBM supply and wafer allocation as the immediate constraints shaping vendor roadmaps. (the-decoder.com)
