UBS flags EMIB-T for Rubin Ultra

UBS said in a May 16 note that a four-chip version of Nvidia's Rubin Ultra could use Intel's EMIB-T packaging rather than Taiwan Semiconductor Manufacturing Co's CoWoS, according to reproductions of the note published by third-party outlets. The line matters because Nvidia has been one of the biggest beneficiaries of TSMC's advanced packaging buildout for AI chips. UBS framed the packaging choice as one factor in Nvidia's gross margin profile through 2027, not as a confirmed product decision by Nvidia. Nvidia has publicly launched the Rubin platform, but it has not publicly detailed Rubin Ultra packaging in the materials reviewed for this article. ### What exactly did UBS say about Rubin Ultra? UBS wrote that Nvidia's "out-year margins" would depend in part on whether it offers "two SKUs for Rubin Ultra," including "2 chip and 4 chip versions," with "the 4 chip version likely using INTC's EMIB-T," according to the reproduced note. That wording appeared in coverage published on May 16 by Let's Data Science and Wccftech. (letsdatascience.com) May 16 is the first date surfaced in the reviewed public reproductions of the UBS language. Reuters could not independently review the full original UBS note from the bank's client portal, and Nvidia, Intel and TSMC packaging plans for Rubin Ultra were not spelled out in the official product pages reviewed here. (letsdatascience.com) ### Why does EMIB-T matter if CoWoS already dominates AI packaging? Intel says EMIB is a 2.5D interconnect approach that uses small bridges embedded in the substrate rather than a full silicon interposer. In a technology brief, Intel said EMIB-T adds through-silicon vias, or TSVs, and said the architecture can support "design conversion from other packaging technologies." Intel also said the approach offers options for logic-to-logic and logic-to-HBM communication. (letsdatascience.com) TSMC describes CoWoS as a core 3DFabric packaging family for AI and supercomputing chips. On its technology page, TSMC says CoWoS-S uses a silicon interposer and supports interposers up to 3.3 times reticle size, while CoWoS-L and CoWoS-R are aimed at larger designs. Those official descriptions do not establish that one packaging method will be used for Rubin Ultra. (intel.com) They do show why analysts are focusing on package architecture as AI accelerators grow larger and integrate more chiplets and HBM memory. ### What has Nvidia actually said in public about Rubin? Nvidia announced the Rubin platform on January 5, 2026, calling it a six-chip platform built around the Vera CPU, Rubin GPU, NVLink 6 switch, ConnectX-9 SuperNIC, BlueField-4 DPU and Spectrum-6 Ethernet switch. (3dfabric.tsmc.com) In its newsroom release, Nvidia said Rubin is designed to cut inference token cost and training time versus Blackwell-based systems. Nvidia's public Rubin materials reviewed here describe the platform and rack-scale systems, including Vera Rubin NVL72 and HGX Rubin NVL8, but they do not specify Rubin Ultra package technology. The company also does not, in those materials, confirm a two-chip and four-chip Rubin Ultra split. ### What has Intel said publicly about EMIB-T? (nvidianews.nvidia.com) Intel presented Foundry Direct Connect 2025 in San Jose on April 29, 2025, and said the event would cover advanced packaging alongside process technology and ecosystem partnerships. Intel's press materials for the event named Cadence, Siemens and Synopsys as partners collaborating on advanced packaging flows. (nvidianews.nvidia.com) Intel's EMIB technology brief says EMIB has been in high-volume manufacturing since 2017 and is used in products across server, network and HPC segments. The same brief says EMIB-T was added to address growing HBM-related power-delivery demands. ### What remains unconfirmed? Nvidia has not publicly confirmed, in the sources reviewed here, that Rubin Ultra will ship in a four-chip EMIB-T version. (newsroom.intel.com) UBS's language, as reproduced publicly, says "likely," which signals analyst expectation rather than a disclosed customer award or a company announcement. (intel.com) TSMC's official CoWoS materials continue to position CoWoS as a packaging platform for AI and supercomputing, and Intel's official materials continue to market EMIB-T for large multi-die designs. The next concrete data point would be a product disclosure from Nvidia, a packaging customer disclosure from Intel, or a roadmap update from TSMC tied to Rubin-class systems. (3dfabric.tsmc.com) (letsdatascience.com)