TSMC CoWoS bottleneck
TSMC’s CoWoS packaging is the choke point — capacity rising from ~35k to 130k wafers/month but still strained, with Nvidia taking about 60% of slots and HBM4/CPO AI chips fighting for space ( ). That packaging limit is the immediate cap on how fast AI accelerators from NVIDIA, AMD and hyperscalers can scale through 2026 (x.com).
Morgan Stanley’s supply-chain note projects Nvidia will book roughly 595,000 CoWoS wafers in 2026 — about 60% of global CoWoS demand — with roughly 510,000 of those to be produced at TSMC. (eu.36kr.com) The same Morgan Stanley modeling splits the remainder of 2026 CoWoS demand with Broadcom/Google-class customers at about 15% and AMD around 11%, leaving limited headroom for other hyperscalers. (semimedia.cc) Tier-1 OSATs are increasing front-end CoWoS work: Commercial Times/TrendForce reporting says ASE’s CoWoS capacity is being expanded toward ~20,000–25,000 wafers per month as TSMC outsources simpler RDL flows to partners. (trendforce.com) HBM4 supply is being allocated alongside packaging: multiple Korean and industry reports show SK hynix and Samsung as the primary HBM4 suppliers for NVIDIA’s Vera/Rubin family, while Korean press and Reuters-syndicated reporting say Samsung has lined up up to 800 million gigabits of HBM4 for OpenAI’s Titan project. ( ) TSMC and investment banks have revised CoWoS ramp timing upward — Morgan Stanley now models monthly CoWoS capacity reaching 120k–130k wafers by end-2026 — and TSMC’s public filings show multi‑$10‑billion capex plans to support packaging growth (Bloomberg reports TSMC earmarked up to $56 billion in 2026 capex). ( ) Even with those ramps, packaging specialization will remain tight through 2026: industry analysts say CoWoS-L qualification (TSMC “super‑carrier”) and OSAT scale-up will relieve pressure only gradually, while Nvidia trials alternate approaches such as CoWoP and package redesigns to reduce substrate dependence. ( )
