AI starts out‑designing engineers, says post

A May 22 post from storage analyst NewMaxx pointed readers to a Tom’s Hardware report that said AI is beginning to out-design chip engineers in narrow parts of the semiconductor workflow. Tom’s Hardware said large language models are accelerating software development for chip design tools, while adding that the gains come “with caveats.” The claim fits a broader push by the largest electronic design automation vendors to move AI from helper software into the core of chip design and verification. Synopsys, Cadence and Siemens are all now selling AI systems that promise faster workflows, more automation and better design outcomes, while each also emphasizes the need for engineer oversight, reproducibility and validation. (tomshardware.com) ### Where is AI actually beating engineers? Cadence says its Cerebrus Intelligent Chip Explorer lets block engineers set power, performance and area goals, then uses AI to optimize the design flow “in a completely automated way.” The company says the tool is designed to improve PPA — shorthand for power, performance and area — and engineering productivity across complex SoC projects. (synopsys.com) Tom’s Hardware described the gains as narrow rather than general. That distinction matters because chip design is not one monolithic task: it includes architecture, RTL creation, floorplanning, placement, routing, timing closure, verification, testbench generation and signoff. The areas where AI is strongest are the ones that can be framed as repeated optimization problems with measurable targets. (cadence.com) ### What are the vendors saying the tools do? Synopsys says its AI copilot is embedded across the design stack and can automate tasks such as RTL and formal testbench generation. The company says users can get a 40% reduction in information retrieval time and a 10-20X reduction in time-to-solution, with workflow guidance and script generation built into the tools. (tomshardware.com) Cadence says its Cerebrus AI Studio can accelerate SoC delivery by 5X to 10X, and that engineers can optimize multiple blocks concurrently instead of tuning flows by hand. Siemens says its EDA AI products are built to orchestrate multi-tool workflows and raise productivity across chip and PCB design. (synopsys.com) ### Why does this favor narrow tasks first? Siemens says chip design differs from consumer AI use because “accuracy is paramount” and because reproducibility, verifiability and traceability are required from schematic through tapeout. The company says engineers cannot rely on a black box and need to understand how the AI reached its decisions. (cadence.com) Those constraints make narrow optimization domains the easiest place for AI to win first. A system can search more design options than a human can manually test, but the result still has to be checked against timing, manufacturability and signoff rules inside established EDA flows. That leaves the engineer in the loop as the person who sets goals, reviews outputs and accepts or rejects tradeoffs. (siemens.com) ### Does this mean engineers get replaced? Synopsys markets its software as a “copilot,” not as a replacement for design teams. Its product page frames the software as expert guidance, assisted creation and faster access to tool knowledge for engineers at different experience levels. Cadence makes a similar point in product language that says designers “always have control” through interactive analysis and run management. (cadence.com) Siemens also stresses that trust and validation are essential before final designs move forward. ### What changes in the workflow if this keeps working? (synopsys.com) The immediate shift is from hand-tuning every step to supervising automated exploration. Engineers still define constraints, choose objectives, inspect tradeoffs and sign off the result, but more of the search work moves into AI-driven tooling. That is the part of the process vendors are now trying to sell as faster, more scalable and more reusable from one project to the next. (cadence.com) Tom’s Hardware published its report on May 22, 2026, and the next concrete checkpoints will come from product rollouts and customer case studies from Synopsys, Cadence and Siemens as those tools move deeper into production design flows. (tomshardware.com) (synopsys.com)