TSMC's roadmap read with caution
- Taiwan Semiconductor Manufacturing Co. laid out a process roadmap through 2029 this week, adding A13, A12 and N2U after its North America Technology Symposium, while Igor’s Lab urged readers not to treat node names as performance facts. - The roadmap pairs different jobs to different nodes: N2U is pitched as a lower-cost N2-family step for 2028, while A12 is a 2029 A14-based extension with Super Power Rail for AI and high-performance chips. - TSMC is stretching families, not just shrinking numbers, as packaging, power delivery and cost now shape deployment as much as transistor scaling. (tsmc.com)
A chip “node” is the manufacturing generation, but the label alone does not tell you how a processor will run in a server or a phone. This week, TSMC extended that point by mapping its process lineup through 2029 with A13, A12 and N2U. (igorslab.de) (trendforce.com) TSMC’s official A14 page says A14 is planned for 2028 and targets up to 15% higher speed at the same power, or up to 30% lower power at the same speed, versus N2. The company says A14 development is ahead of schedule on yield. (tsmc.com 1) (tsmc.com 2) TSMC’s A16 page shows why the node name is only part of the story. A16 adds Super Power Rail, a backside power-delivery scheme that frees front-side wiring for signals and cuts IR drop, which is voltage loss inside the chip. (tsmc.com) That power-delivery change is aimed at high-performance computing parts with dense wiring and heavy current draw, not at every chip category. TSMC says A16 can deliver 8% to 10% more speed at the same voltage, or 15% to 20% lower power at the same speed, versus N2P. (tsmc.com) The new 2026 roadmap pushes that segmentation further. Igor’s Lab reports A13 as a 2029 follow-on to A14, A12 as a 2029 A14-based extension with Super Power Rail, and N2U as a 2028 extension inside the N2 family. (igorslab.de) TrendForce, citing TSMC and Tom’s Hardware, says N2U is meant as a lower-cost upgrade path for N2-class designs, while A12 is positioned for data-center and high-performance computing products. The same report says A16 volume production is now slated for 2027. (trendforce.com) TSMC’s own 2025 symposium release made the same broader point from the packaging side. The company said it plans 9.5-reticle CoWoS packaging for volume production in 2027, enough to integrate 12 high-bandwidth-memory stacks or more with leading-edge logic. (tsmc.com) That matters because many artificial-intelligence chips are now constrained by memory bandwidth, package size and power delivery as much as by transistor density. TSMC’s 2025 release also said its SoW-X wafer-scale system is scheduled for volume production in 2027. (tsmc.com) Igor’s Lab also draws a line between official roadmap items and rumor. The site says A13, A12 and N2U were formally introduced, while “sub-1-nm” test production starting in 2029 remains a media report rather than a product node confirmed with the same clarity. (igorslab.de) The practical read is that TSMC is no longer selling one ladder where every smaller number cleanly replaces the last. It is selling a menu of process, power and packaging options, and the best choice depends on the chip’s workload, cost target and design reuse. (igorslab.de) (tsmc.com)
