AMD commits $10B to Taiwan packaging
- AMD said on May 21 it will invest more than $10 billion in Taiwan to expand advanced packaging and AI chip manufacturing partnerships. - AMD said “Venice,” its next-generation EPYC processor, has entered production ramp on TSMC’s 2nm process, with future production also planned in Arizona. - AMD said Helios rack-scale systems using Venice and Instinct MI450X remain on track for multi-gigawatt deployments in the second half of 2026.
Advanced Micro Devices said on May 21 it will invest more than $10 billion across Taiwan’s semiconductor ecosystem, tying the spending to advanced packaging capacity and partnerships needed for next-generation AI infrastructure. The company announced the plan alongside a second update: production ramp has begun in Taiwan for its next-generation EPYC server processor, code-named Venice, on Taiwan Semiconductor Manufacturing Co.’s 2-nanometer process. AMD said the moves are aimed at scaling the manufacturing stack behind AI systems, not just the leading-edge wafer node. ### Why is AMD putting so much money into Taiwan now? AMD said the spending will go toward expanding strategic partnerships and scaling advanced packaging manufacturing for AI infrastructure in Taiwan. In its release, the company linked the investment to demand for AI systems and said it would work across the local ecosystem rather than treat chip production as a foundry-only issue. (amd.com) Reuters reported on May 21 that AMD described the plan as an investment in Taiwan’s AI sector to deepen partnerships and increase its ability to build and assemble advanced AI chips. That framing puts packaging and assembly alongside wafer fabrication in AMD’s current expansion plans. ### What exactly did AMD announce on packaging? (amd.com) AMD said the Taiwan investment will support “EFB-based 2.5D packaging” for 6th-generation EPYC processors, including Venice. The company said that packaging approach is intended to deliver higher interconnect bandwidth and better efficiency, two metrics that have become central as AI systems combine CPUs, GPUs and high-bandwidth memory in tighter configurations. (msn.com) CNBC reported in April that Nvidia had reserved most of TSMC’s most advanced packaging capacity and that advanced packaging had become a bottleneck for AI chip supply. AMD did not cite Nvidia in its release, but the broader industry context described by CNBC helps explain why packaging capacity has become a strategic target for chip companies competing in AI infrastructure. (amd.com) ### What is Venice, and why does the 2nm ramp matter? AMD said Venice is its next-generation EPYC processor and the first high-performance computing product in the industry to reach production ramp on TSMC’s advanced 2nm technology. The company said the ramp marks a milestone in its collaboration with TSMC and added that future production is planned at TSMC’s Arizona fabrication facility. (cnbc.com) The same announcement said AMD is also preparing a follow-on product called Verano, which it described as a successor to Venice with LPDDR integration aimed at rising memory demand from agentic AI workloads. AMD did not give a launch date for Verano in the release. ### Which Taiwan partners are visible in this push? AMD’s press release did not list every supplier in the Taiwan expansion summary returned in search results, but outside coverage on May 21 pointed to packaging partners including ASE and SPIL as visible beneficiaries of the program. (amd.com) Reuters’ summary and AMD’s own release both focused on ecosystem investment and packaging scale-up, while secondary reports tied those efforts to named outsourced semiconductor assembly and test companies in Taiwan. TrendForce reported on May 21 that Lisa Su was also expected to visit TSMC in connection with 2nm capacity. AMD’s official statement separately confirmed only that Venice is ramping in Taiwan now and that Arizona production is planned later. ### What comes next for AMD’s AI systems buildout? (amd.com) AMD said its Helios rack-scale platform, which combines Venice CPUs with Instinct MI450X GPUs, remains on track for multi-gigawatt deployments beginning in the second half of 2026. That gives the next milestone in the company’s timetable after the Taiwan packaging investment and Venice production ramp. (trendforce.com) TSMC’s role also extends beyond this week’s announcement. AMD said future Venice production is planned at TSMC’s Arizona fab, while the current 2nm ramp is underway in Taiwan. Those two sites are the named manufacturing locations AMD has attached to the program so far. (amd.com 1) (amd.com 2)