Hyperscalers building custom silicon
Multiple briefings note hyperscalers and startups (Groq, AMD, Intel, Meta and others) are accelerating custom‑chip efforts to challenge NVIDIA’s dominance reported reported. That trend is creating more demand for portable IP and second‑source accelerator options.
Meta said it will develop and deploy four new generations of its Meta Training and Inference Accelerator (MTIA) chips within the next two years (about.fb.com). Meta also disclosed it already deploys “hundreds of thousands” of MTIA chips for inference across its apps and ads workloads. (about.fb.com) AMD and Meta announced a multi‑year agreement to deploy up to 6 gigawatts of AMD Instinct GPUs, announced Feb. 24, 2026. (ir.amd.com) The AMD deal includes a co‑engineered MI450‑based accelerator, a Helios rack architecture, and a performance‑based warrant for up to 160 million AMD shares, with initial gigawatt shipments slated in H2 2026. (marketbeat.com) Nvidia agreed to license Groq’s inference technology and acquire Groq assets for about $20 billion in a deal reported Dec. 24, 2025, with Groq’s CEO and other senior leaders moving to Nvidia. (cnbc.com) Groq had raised $750 million at a roughly $6.9 billion valuation in September 2025, a funding round that preceded the licensing/asset transaction. (money.usnews.com) Google’s seventh‑generation TPU, dubbed Ironwood, began public rollouts in late 2025 and Google claimed it is more than four times faster than the prior generation. (blog.google) AWS unveiled Trainium3 and Nova2 at re:Invent 2025 and industry trackers say AWS is scaling in‑house silicon across large clusters; TrendForce and others report ASIC shipments and hyperscaler ASIC deployments growing sharply in 2025–26. (aboutamazon.com) Microsoft published Maia 200 as a dedicated inference accelerator on Jan. 26, 2026, listing TSMC 3nm process, 216GB HBM3e and 7 TB/s memory bandwidth in its spec sheet. (blogs.microsoft.com) Suppliers are shipping more portable IP and interconnect blocks to meet hyperscalers’ multi‑vendor stacks: Synopsys announced Ultra Ethernet IP for up to 1.6 Tbps and UALink accelerator link IP up to 200 Gbps per lane to stitch large accelerator fabrics. (datacenterdynamics.com) Market trackers and reporting show hyperscalers locking multi‑gigawatt semiconductor capacity and co‑design partnerships in early 2026 as they diversify suppliers and build redundancy. (epium.com) RISC‑V momentum for AI continues with ecosystem bodies and vendors pushing AI‑centric extensions and IP; the RISC‑V AI Market Development Committee highlighted server‑grade RISC‑V use cases in 2025. (riscv.org) Commercial RISC‑V IP vendors like SiFive launched the Intelligence XM series — a scalable RISC‑V matrix engine that the company says delivers up to 16 TOPS (INT8) or 8 TFLOPS (BF16) per GHz per cluster — positioning RISC‑V as a portable option for custom accelerator stacks. (datacenterdynamics.com)
