TSMC Raises Packaging Stakes
- Taiwan Semiconductor Manufacturing Co. used its April 22 North America Technology Symposium in Santa Clara to launch A13, a follow-on process due in 2029, and confirm an Arizona packaging plant. - TSMC said A13 shrinks A14 designs by about 6% while keeping A14 design rules compatible, and Kevin Zhang said Arizona will add CoWoS and 3D-IC packaging before 2029. - Packaging, not transistor scaling alone, is now the near-term constraint for AI chips, with Nvidia-style multi-die designs driving demand for bigger CoWoS systems. (reuters.com)
Modern artificial intelligence chips are often several silicon pieces wired together inside one package, not one slab of silicon. On April 22, Taiwan Semiconductor Manufacturing Co. said it will add that packaging step in Arizona before 2029 while introducing its next A13 process. (reuters.com) (pr.tsmc.com) TSMC unveiled A13 at its 2026 North America Technology Symposium in Santa Clara, California. The company said A13 is a direct shrink of A14 and is scheduled for production in 2029, one year after A14. (pr.tsmc.com) TSMC said A13 delivers 6% area savings from A14, keeps full design-rule and electrical compatibility with A14, and adds power-efficiency and performance gains through design-technology co-optimization. TSMC also previewed A12, another 2029 technology aimed at artificial intelligence and high-performance computing. (pr.tsmc.com) (datacenterdynamics.com) Packaging is the step that connects compute dies and high-bandwidth memory into one working module. Reuters reported that this step has become a supply bottleneck for Nvidia and other companies building advanced AI accelerators. (reuters.com) Kevin Zhang, TSMC deputy co-chief operations officer and senior vice president, said construction has begun in Arizona. He told Reuters the site will add CoWoS and 3D-IC capability before 2029, so chips made in Arizona will no longer need to return to Taiwan for that stage. (reuters.com) TSMC’s own roadmap shows why the packaging step is getting equal billing with the process node. The company said a 14-reticle CoWoS package capable of combining about 10 large compute dies and 20 HBM stacks is slated for production in 2028. (pr.tsmc.com) TSMC is also stretching its lithography roadmap without ASML’s newest high-NA extreme-ultraviolet tools. Kevin Zhang told Reuters the company can keep scaling through 2029 with existing EUV systems, which Bloomberg reported cost more than €350 million each in the high-NA version. (reuters.com) (bloomberg.com) That leaves TSMC selling customers two things at once: smaller transistors and larger assemblies. In the AI market of 2026, the second piece is increasingly the one that decides how many accelerators can actually ship. (reuters.com) (pr.tsmc.com)
