AMD Medusa leak hints Zen 6 gains
An industry leak on Medusa Point suggests Zen 6 will boost IPC and introduce a 32MB L3 cache configuration—changes that could raise performance per watt and reduce reliance on raw clock speed (tech.yahoo.com). The takeaway for builders: Zen 5 is still strong today, but laptop and desktop refreshes in 2026 may favor cache/IPC improvements over chasing higher clocks (tech.yahoo.com).
A public Geekbench entry lists the sample under OPN 100-000001713-31 on a platform named Plum‑MDS1, identifying it as a Medusa Point engineering part rather than shipping silicon ( ). The listing reports a 10‑core, 20‑thread configuration with about 10 MB of L2 cache—roughly 1 MB per core—according to the leaked hardware data ( ). Clock figures in the entry show a 2.40 GHz base frequency on paper while actual runs recorded roughly 2.0–2.1 GHz (and some early reports noted lower transient clocking), a pattern consistent with pre‑production engineering samples running at constrained voltages/power during test validation ( ). Independent outlets noted the sample produced Geekbench results that approximate current‑generation scores despite those low clocks, with at least one analysis describing parity at far lower operating frequency than equivalent Zen 5 parts in the same benchmarks ( ). The public listing and follow‑up writeups call out signs of hybrid core mapping and show strings hinting at FP16/AVX‑VNNI support, which analysts interpret as preliminary indicators of expanded on‑device AI and mixed core strategies in Medusa Point silicon ( ). Multiple reporters emphasize the sample is early test silicon and place a consumer‑timing window around early 2027 (CES 2027 territory), noting testing is already underway but that final clocks, power targets and core counts could change before any retail launch ( ).
