Packaging and substrate are the new choke points

The chip shortage story has moved one step down the assembly line. The squeeze is no longer just about making the silicon die; it is now about wrapping that die into a package big enough to hold memory, power, and thousands of tiny connections. (cnbc.com) Nvidia has reserved most of Taiwan Semiconductor Manufacturing Company’s top-end packaging capacity, according to CNBC, which means one customer is now absorbing much of the industry’s scarcest finishing step. Taiwan Semiconductor Manufacturing Company’s North America packaging head told CNBC its Chip on Wafer on Substrate capacity is growing at an 80% compound annual rate. (cnbc.com) Chip on Wafer on Substrate is a way to bolt several pieces of silicon together on one base, like mounting an engine, battery, and cooling system onto the same chassis instead of shipping them as separate parts. Taiwan Semiconductor Manufacturing Company says the method is built for artificial intelligence and supercomputing chips that need very high integration density. (tsmc.com) That base is the substrate, which is the dense circuit board under the chip package that carries signals and power in and out. Taiwan Semiconductor Manufacturing Company says its Chip on Wafer on Substrate platform can use very large interposers and support more than four stacks of high-bandwidth memory, which is why the package keeps getting physically larger and electrically more demanding. (tsmc.com) A big share of those high-end substrates use Ajinomoto Build-up Film, an insulating layer that lets manufacturers stack fine wiring in many layers without shorting out. Ajinomoto says the material sits inside substrates for high-performance central processing units, which is why the whole segment is usually called the Ajinomoto Build-up Film substrate market. (ajinomoto.com) Now the pinch is spreading from the package houses to the materials underneath them. DigiTimes reported on April 8 that tighter supply of glass-fiber cloth, copper foil, and drilling capacity could push the Ajinomoto Build-up Film substrate market into a multi-year upcycle as artificial intelligence customers demand more layers and more capacity. (digitimes.com) DigiTimes had already reported in February that Taiwan substrate makers were bracing for a 10% to 20% supply gap in T-glass material in 2026. The same reporting said customers were pursuing long-term contracts to lock in capacity before shortages got worse. (digitimes.com) That detail matters because substrate capacity does not expand as fast as wafer capacity. Adding output means more specialty materials, more laser and mechanical drilling, and more yield tuning on boards with extremely fine lines, so a shortage in one input can slow the whole chain. (digitimes.com) (ajinomoto.com) The United States is only now trying to build more of this finishing step at home. CNBC reports that Taiwan Semiconductor Manufacturing Company is adding advanced packaging in Arizona and Intel is ramping packaging in the United States, but most of the world’s advanced packaging still sits in Asia today. (cnbc.com 1) (cnbc.com 2) So the new risk for 2026 is not only “Can the industry print enough leading-edge chips?” It is also “Can the industry package them, wire them, and source the substrate layers underneath them before Nvidia, memory vendors, and custom artificial intelligence chip buyers consume the queue.” (cnbc.com) (digitimes.com)