Packaging scarcity persists
- Advanced packaging capacity is failing to keep up with AI‑chip demand, turning packaging into a program constraint. - Goldman models TSMC’s CoWoS capacity rising to 1.275m wafers in 2026 and 2.49m in 2027. - Multiple market reports say shortages will likely persist beyond 2027, keeping package access a gating assumption for chip programmes ( ).
The bottleneck in artificial-intelligence chips is no longer just making the silicon; it is getting the chips packaged fast enough to ship. (tsmc.com, epoch.ai) That packaging step is called CoWoS, short for Chip-on-Wafer-on-Substrate. TSMC says the technology links a main processor with stacks of high-bandwidth memory inside one package, letting AI accelerators move data at the speeds training systems need. (tsmc.com) Goldman Sachs said this week that TSMC’s CoWoS capacity is now modeled at 1.275 million wafers in 2026 and 2.49 million wafers in 2027, and used that expansion to lift its outlook for Taiwan packaging-equipment suppliers. Investing.com reported the note on April 22, 2026. (investing.com) Even with that buildout, supply is still trailing demand. TSMC told investors on its April 16, 2026 earnings call that AI demand remains strong, while outside market reports in April said CoWoS shortages are likely to last into 2027 and beyond. (tsmc.com, wccftech.com, tweaktown.com) That changes where chip programs get stuck. A designer can have a finished graphics processor or custom AI die, but without a slot in advanced packaging and enough memory stacks, the part cannot be assembled into a sellable product. (epoch.ai, tsmc.com) Epoch AI estimated that the four largest AI-chip designers — Nvidia, Google, AMD, and Amazon — consumed around 90% of global CoWoS capacity in 2025, while using only about 12% of advanced logic-die production. Its March 12, 2026 analysis concluded that packaging and memory, not logic wafers, were the main production constraints last year. (epoch.ai) The pressure is spilling across the supply chain. TrendForce reported this month that TSMC is pushing newer packaging lines such as Chip-on-Panel-on-Substrate, or CoPoS, while industry reports cited by TrendForce and other outlets point to outsourced assembly and test companies taking a larger share of overflow work. (trendforce.com, trendforce.com) TSMC’s latest annual filing says it served 534 customers and manufactured 12,682 products in 2025 across process, specialty, and advanced-packaging services. In this market, that last category has become a scheduling problem as much as a manufacturing one. (tsmc.com) For AI-chip buyers, the practical question is no longer only whose design wins. It is who can secure packaging capacity early enough to turn wafers into working systems. (epoch.ai, tsmc.com)
