Nvidia to source advanced package components from multiple foundries to ease capacity crunch
- Nvidia is reportedly planning to split production of its 2028 Feynman AI GPUs between Taiwan Semiconductor Manufacturing Co. and Intel Foundry, using Intel for some I/O and packaging work. - The reported split would keep the main compute die at TSMC while shifting about 25% of Feynman’s value to Intel 18A or 14A processes and EMIB packaging. - The move points to AI chipmakers spreading packaging risk beyond TSMC as demand for advanced multi-die assembly stays tight. (notebookcheck.net)
Modern AI chips are no longer one slab of silicon. They are built like a small circuit board in a single package, with compute dies, memory stacks and input-output logic stitched together. (intel.com) (tsmc.com) That assembly step is now a bottleneck. Taiwan Semiconductor Manufacturing Co.’s CoWoS packaging has become a choke point for AI accelerators because it links graphics processors to high-bandwidth memory in one dense module. (tsmc.com) A DigiTimes report, cited Saturday by Notebookcheck, says Nvidia plans to divide that work on its 2028 Feynman generation instead of leaving nearly all of it with TSMC. (notebookcheck.net) Under that reported plan, Nvidia would keep the main Feynman graphics die at TSMC but move some I/O die production to Intel Foundry on Intel 18A or 14A. Notebookcheck said the report points to a 75%-25% split between TSMC and Intel. (notebookcheck.net) The packaging split matters because the package now determines how many chiplets and memory stacks a vendor can ship, not just how fast a single die runs. Intel’s Embedded Multi-die Interconnect Bridge, or EMIB, uses small silicon bridges inside the package to connect dies. (intel.com) TSMC’s CoWoS takes a different route, placing chips on wafer-based substrates and linking them to high-bandwidth memory in the same package. Both approaches are advanced assembly methods, but they rely on different factories, tools and supply chains. (tsmc.com) (intel.com) Nvidia has already mapped Feynman as the generation after Rubin on its data-center roadmap. That makes the reported Intel tie-up less about a near-term product launch than about reserving manufacturing options years before volume production. (nvidia.com) (notebookcheck.net) Neither Nvidia nor Intel announced the arrangement in the materials reviewed here, so the details remain a supply-chain report rather than a confirmed contract. The reported direction is still clear: the hardest part of AI-chip scaling is increasingly the package around the silicon, not just the silicon itself. (notebookcheck.net)
