TSMC unveils CoWoS roadmap targeting 24‑high HBM5E stacks

Modern AI chips are no longer limited by the silicon die alone. TSMC is now planning packages so large that the package itself becomes part of the system design. (tsmc.com) (igorslab.de) At its North America Technology Symposium in Santa Clara on April 22, 2026, Taiwan Semiconductor Manufacturing Co. extended its CoWoS roadmap through 2029. The plan pushes beyond 14 reticle-sized package assemblies for AI and high-performance computing chips. (tsmc.com) (igorslab.de) CoWoS stands for Chip on Wafer on Substrate. In plain terms, it is a way to place compute dies and high-bandwidth memory side by side on a shared base so they can trade data faster than they could across a standard circuit board. (tsmc.com) TSMC’s current public CoWoS page says CoWoS-S supports interposers up to 3.3 reticle size, or about 2,700 square millimeters, and points larger designs to CoWoS-L or CoWoS-R. The new roadmap stretches that scale far past today’s published limits. (tsmc.com) (taipeitimes.com) The company’s 2029 target is a CoWoS package with more than 14 reticles and as many as 24 HBM5E stacks, according to reports from the symposium. Tom’s Hardware and Igor’sLAB both said TSMC tied that package class to roughly 48 times more compute and 34 times more memory bandwidth than current designs. (igorslab.de) (technewstube.com) That is a sharp jump from last year’s roadmap. Coverage of TSMC’s 2025 symposium described a 2027 CoWoS-L target at 5.5 reticles with up to 12 HBM3E or HBM4 stacks. (techpowerup.com) (trendforce.com) TSMC is also pairing the bigger package story with a bigger wafer-scale story. Taipei Times reported that a 14-reticle CoWoS design could integrate about 10 large compute chips and 20 HBM stacks, while TSMC’s SoW-X wafer-scale packaging is also slated for 2029. (taipeitimes.com) The pressure behind this roadmap is memory hunger. AI accelerators now need more HBM stacks, more die-to-die links, and more power delivery in the same package, so packaging limits can cap performance before transistor scaling does. (tsmc.com) (futurumgroup.com) That is why TSMC presented packaging alongside new process nodes such as A13, A12, and N2U. The roadmap treats advanced packaging, backside power delivery, and chiplet assembly as one design problem for 2028 and 2029 products. (igorslab.de) (tomshardware.com) The practical message is that future AI chips will be drawn around package area, memory placement, and thermal limits from the start. By 2029, the package is no longer the box around the chip. (tsmc.com) (igorslab.de)