AMD launches Ryzen AI Embedded P100
AMD unveiled the Ryzen AI Embedded P100 Series for industrial edge use — claiming a 'Triple‑Threat Architecture' with up to 2× CPU cores and ~36% higher system TOPS for robotics and 3D health imaging announced. The chip targets the same industrial edge domain where hardware/software co‑design and power efficiency matter most.
AMD announced)) the Ryzen AI Embedded P100 family on January 5, 2026, saying 4–6 core P100 models were sampling with production shipments expected in Q2 2026. (ir.amd.com) AMD formally launched)) higher-tier P100 SKUs in early March 2026 at Embedded World, adding 8‑, 10‑ and 12‑core parts (model names include P164, P174, P185 and industrial “i” variants). (phoronix.com) The expanded P100 hardware pairs up to 12 Zen 5 CPU cores with an RDNA 3.5 GPU and an XDNA2 NPU inside a compact 25×40 mm BGA package, and the lineup is specified across a 15–54 W operating range with 16 PCIe Gen4 lanes. (ir.amd.com) AMD quantified)) the initial P100 4–6 core parts at up to 50 TOPS of NPU performance, while independent reporting on the 8–12 core SKUs cites combined system figures as high as ~80 TOPS for certain configurations. (ir.amd.com) The P100 family is rated for continuous 24/7 use with support for –40 °C to +105 °C environments and a 10‑year BGA lifecycle, and AMD indicated silicon for the new 8–12 core variants is slated for Q3 2026 with reference boards due in H2 2026. (ir.amd.com) AMD has certified the RDNA 3.5 iGPU for ROCm and ships a Xen‑based reference stack that isolates Yocto/Ubuntu application domains and FreeRTOS real‑time domains for mixed‑criticality systems. (phoronix.com) OEM and module partners already listed around the P100 rollout include Advantech, congatec, Kontron and SolidRun (with COM Express Type 6 modules announced to host up to 12‑core P185 SoCs), indicating available board and module pathways for rapid prototyping and system integration. (hexmojo.com) AMD framed the single‑chip integration of Zen 5 CPU + RDNA 3.5 GPU + XDNA2 NPU as a way to collapse board‑level BOM and enable deterministic, low‑latency mixed‑criticality workloads in automotive and industrial systems, positioning vendors to co‑design firmware, OS, and ML stacks around a common BGA compute substrate. (ir.amd.com)
