AMD, Intel make memory and CPU moves
AMD struck an MoU with Samsung on HBM4 supply and foundry collaboration that supports AMD Instinct roadmap claims, while Intel shipped Arrow Lake improvements that sharpen CPU+accelerator messaging. Both moves give customers alternatives to GPU‑first stacks. (simplywall.st) (xda-developers.com)
The memorandum was signed on March 18, 2026 at Samsung’s Pyeongtaek complex and was attended by AMD Chair and CEO Dr. Lisa Su and Samsung Vice Chairman & CEO Young Hyun Jun. (semiconductor.samsung.com)) Under the agreement Samsung will align on primary HBM4 supply for AMD’s next‑generation Instinct MI455X accelerator and provide advanced DDR5 for AMD’s 6th‑Gen EPYC “Venice” processors and the AMD Helios rack platform. (semiconductor.samsung.com)) Samsung describes its HBM4 as built on a 6th‑generation 10‑nm‑class DRAM process with a 4nm logic base die, offering per‑pin speeds up to 13 Gbps and an aggregate bandwidth up to 3.3 TB/s. (semiconductor.samsung.com)) Intel’s Arrow Lake “Plus” refresh arrives as the Core Ultra 200S Plus lineup with the Core Ultra 7 270K Plus (24 cores: 8P+16E) and Core Ultra 5 250K Plus (18 cores: 6P+12E), priced respectively at $299 and $199 for desktop SKUs. (xda-developers.com)) Intel says the refresh boosts die‑to‑die / memory controller speeds by up to 900 MHz, adds native DDR5‑7200 and quad‑rank CUDIMM support, and ships a Binary Optimization Tool aimed at extracting better CPU and CPU+accelerator performance. (tomshardware.com)) Samsung’s HBM4 bandwidth figures for MI455X and Intel’s memory‑and‑latency focused Arrow Lake Plus changes both supply concrete hardware pathways—high‑bandwidth HBM4 for AMD accelerators and lower‑latency, higher‑speed DDR5 for Intel CPUs—that customers can weigh against GPU‑first stacks when architecting training and inference systems. (semiconductor.samsung.com))
