ASML's High-NA EUV Is Ready
ASML announced its next-gen High-NA EUV lithography is officially ready for high-volume manufacturing. The milestone was reached after successfully exposing over 500,000 wafers with partners, a critical step that could significantly accelerate advanced node production for future Apple Silicon.
Intel is the first to install the production model, the ASML Twinscan EXE:5200B, at its Oregon facility. The company has confirmed it will deploy High-NA EUV for its upcoming 14A fabrication process, aiming to reclaim process leadership. The new 0.55 numerical aperture optics enable printing at an 8nm resolution in a single exposure, a major advance over the 13nm limit of previous Low-NA EUV tools. This allows for transistors that are 1.7 times smaller and can nearly triple transistor density, a key enabler for sub-2nm process nodes. This capability comes at a steep price, with each machine costing between $380 million and $400 million—roughly double the cost of current EUV systems. A significant technical challenge is the smaller exposure field size, which is half that of Low-NA tools and may require complex "stitching" for larger chip designs, introducing potential yield and overlay error risks. The foundry adoption strategy is fragmented. While Intel is the lead adopter, key Apple supplier TSMC is notably holding off, planning to extend existing multi-patterning techniques before integrating High-NA for its 1.4nm node, citing the high cost. Samsung and SK Hynix have also placed orders and received initial tools for R&D and future production. Full integration into high-volume manufacturing lines will not be immediate. Customers will likely require 2-3 years for extensive testing and process development. Mass production using the High-NA platform is broadly expected to commence in the 2026-2027 timeframe.
