ASML Scanners Remake 3D Chip Packaging
A new deep analysis shows ASML's High-NA EUV and TWINSCAN scanners are solving critical wafer warping issues for 3D chiplet packaging. This technology is becoming essential for producing next-gen AI chips and is reshaping the competitive landscape for advanced packaging equipment.
Wafer warping is a significant hurdle in 3D packaging, where stacked dies can cause stress and deformation, impacting yield. ASML's new TWINSCAN XT:260 is designed to handle warped wafers up to 1 mm. This capability, combined with its through-silicon alignment, is critical for advanced packaging techniques like TSMC's CoWoS and Intel's Foveros. The XT:260 uses i-line lithography at a 365 nm wavelength, achieving a resolution of around 400 nm. While not as fine as EUV, this is optimized for the larger features in packaging. Its dual-stage platform, which exposes one wafer while aligning the next, enables a throughput of up to 270 wafers per hour, a fourfold productivity increase over existing packaging lithography tools. This new focus on advanced packaging signals a strategic shift for ASML, blurring the lines between front-end and back-end semiconductor manufacturing. The company is leveraging its expertise in high-precision optics and wafer handling to address the growing complexity of chiplet integration. This move positions ASML as a key player in the entire semiconductor value chain, not just front-end lithography. On the leading edge of fabrication, ASML's High-NA EUV systems, like the Twinscan EXE, cost around $380 million to $400 million per unit. These machines are massive, weighing 150,000 kilograms, and require 250 engineers and six months to assemble. They enable printing of circuit patterns down to 8nm, a 1.7x reduction from previous EUV tools, which is crucial for sub-3nm process technologies. Intel has been an early adopter of High-NA EUV, installing the industry's first commercial tool and aiming to use it for its post-18A (1.8nm-class) process technology. Other major players like Samsung and SK Hynix have also placed orders, with Samsung targeting logic and SRAM production and SK Hynix focusing on HBM memory. However, TSMC has expressed concerns about the high cost and may delay adoption until its 1nm-class node around 2030. The competitive landscape for packaging equipment includes established back-end players like Applied Materials, Lam Research, and Veeco Instruments. While ASML holds a monopoly on EUV, its expansion into packaging pits it against companies with extensive experience in deposition, etching, and bonding. Dutch firm Besi, a leader in hybrid bonding, is another key player, though its technology is currently seen as complementary to ASML's lithography.