Altera Agilex 9 Targets Edge RF
Altera's new Agilex 9 SoC FPGA Direct RF-Series integrates wideband data converters with direct RF sampling up to 64 Gsps. Built on a 10nm process, the chip is designed for applications with severe size, weight, and power (SWaP) constraints, such as modern avionics and sensor fusion systems.
- The Intel 10nm process used is specifically the "SuperFin" technology, which provided a performance improvement of 17-18%, an enhancement Intel claimed was comparable to a full-node transition. This was achieved by redesigning the FinFET transistor and using a new SuperMIM (metal-insulator-metal) capacitor that increased capacitance fivefold. - Its architecture is a chiplet-based design that uses an Embedded Multi-Die Interconnect Bridge (EMIB) to integrate the data converters and FPGA die into a single package. This approach enables up to 25 TFLOPS of digital signal processing performance (FP16). - The direct RF sampling approach simplifies the entire signal chain by reducing the need for external analog components like mixers and filters, which in turn reduces latency, power consumption, and potential sources of noise. One customer noted that this integration helped to "shrink a refrigerator-sized piece of equipment down to a Rubik Cube". - The SoC includes a quad-core 64-bit Arm Cortex-A53 processor subsystem running at up to 1.4 GHz. It also features high-speed transceivers capable of data rates up to 58 Gbps using PAM4 modulation. - Altera, now operating as a standalone company after being spun off from Intel in early 2024, has moved the Agilex 9 into volume production. Intel originally acquired Altera in 2015 for $16.7 billion. - Third-party hardware support is available, including a development kit (AGRW027) with eight ADC/DAC channels and 400 GbE connectivity, as well as palm-sized modules from partners like Annapolis Micro Systems for edge sensor applications. - The product line includes variations such as a medium-band device with 20 ADC channels (4 Gsps), 16 DAC channels (12 Gsps), and a 2.7 million logic element FPGA fabric.
