TSMC's US packaging push

TSMC plans to add an advanced chip-packaging plant in Arizona by 2029, extending its U.S. buildout beyond wafer-making fabs. (reuters.com) Chief Executive C.C. Wei said on April 22 that TSMC wants “as complete a supply chain as possible” in Arizona, where the company is already building multiple fabrication plants. Reuters reported the packaging site would handle the step that links several chips into one higher-performance package, a design used in modern Nvidia artificial-intelligence processors. (reuters.com) Packaging is the back-end stage after wafers are made: the silicon dies are cut, connected, stacked or placed side by side, and sealed so they can work as one product. TSMC said at its North America Technology Symposium that the Arizona expansion will sit alongside new process plans including N2U in 2028 and A13 in 2029. (tomshardware.com) The U.S. push still leaves a long runway. The packaging plant is targeted for 2029, years after TSMC’s first Arizona fab starts volume production, so it does not create a full domestic chip stack in the near term. (reuters.com) TSMC also used the event to show how it is stretching its roadmap without adopting ASML’s newest high-numerical-aperture extreme ultraviolet machines before 2029. C.C. Wei said the tools are “too expensive” for now, and Reuters reported TSMC believes it can keep shrinking chips with existing equipment and process changes. (reuters.com) TSMC’s published targets were incremental, not a reset. The company said A13 should deliver up to 10% to 15% speed improvement at the same power, or 25% to 30% lower power at the same speed, plus about 1.2 times logic density versus A14; Tom’s Hardware reported A12 is planned for 2029 and A16 slipped to 2027. (finance.yahoo.com) (tomshardware.com) That matters for customers building artificial-intelligence chips, because performance now depends on both the transistor technology and the way multiple dies are stitched together. Reuters reported that advanced packaging capacity has become a bottleneck across the industry as companies race to ship larger AI accelerators. (reuters.com) TSMC is not walking away from Europe’s lithography leader; it is delaying the priciest option. Reuters reported ASML’s high-NA machines cost about $380 million each, and TSMC said it does not expect to need them for A14 or A13 production before the end of the decade. (reuters.com) The result is a slower version of semiconductor localization than Washington has pushed for since the CHIPS Act. More of the work will move to Arizona, but the timetable TSMC laid out on April 22 points to a staged buildout, with packaging, leading-edge logic, and tool choices all constrained by cost and timing. (reuters.com)