Packaging Is The Bottleneck
Advanced chip packaging — the step after wafer fabrication that assembles dies, memory and interconnect — is emerging as the likely chokepoint for AI hardware supply, rather than wafer fabs alone. (cnbc.com) The story notes Nvidia has reserved most of TSMC’s advanced packaging capacity as TSMC expands in the U.S., which shifts where system-level differentiation and supply risk live. (cnbc.com)
For years, people treated chip shortages like a wafer problem: not enough factories carving circuits into silicon. This week’s surprise is that one of the tightest choke points is the step after that, where those pieces get turned into a working artificial intelligence chip, and Nvidia has already reserved most of Taiwan Semiconductor Manufacturing Company’s top capacity there. (cnbc.com) Think of a modern artificial intelligence processor less like one giant engine block and more like a high-performance car assembled from several precision parts. Advanced packaging is the factory step that connects the compute dies, memory, power delivery, and wiring into one finished unit that a server can actually use. (cnbc.com) That step got more important because the biggest artificial intelligence chips no longer fit neatly on one piece of silicon. Taiwan Semiconductor Manufacturing Company’s CoWoS, short for Chip on Wafer on Substrate, is built for exactly this job: placing several dies together and linking them through a silicon interposer inside one package. (tsmc.com) The memory is part of the squeeze. Nvidia’s H200 uses 141 gigabytes of high-bandwidth memory and 4.8 terabytes per second of memory bandwidth, which means the package has to place memory extremely close to the processor and move data across very short, very dense connections. (nvidia.com) So even if a wafer fab makes the compute die on time, the finished product can still be late if packaging slots are full. Georgetown University’s John VerWey told CNBC that packaging can become a bottleneck quickly if companies do not keep spending ahead of the surge in fab output coming over the next few years. (cnbc.com) Taiwan Semiconductor Manufacturing Company told CNBC its most advanced packaging line is growing at an 80% compound annual growth rate. That is a huge expansion number, but it also tells you how fast demand for these multi-die artificial intelligence parts has outrun the old packaging model. (cnbc.com) The geography matters almost as much as the technology. CNBC reported that almost all of this advanced packaging still happens in Asia, which means a chip whose wafers are made in the United States can still need a round trip across the Pacific before it becomes a finished accelerator card. (cnbc.com) That is why Arizona is suddenly about more than wafer fabs. Taiwan Semiconductor Manufacturing Company said on March 4, 2025 that its planned United States investment would rise to $165 billion and include two advanced packaging facilities in Phoenix alongside new fabrication plants and a research center. (tsmc.com) Intel is trying to turn that gap into an opening. Its Embedded Multi-die Interconnect Bridge, or EMIB, has been in high-volume manufacturing since 2017 and connects multiple dies with small silicon bridges embedded in the package substrate instead of one large interposer. (intel.com) CNBC says Intel already packages chips for Amazon and Cisco, and on April 7 Elon Musk committed Intel packaging work for custom chips planned for SpaceX, xAI, and Tesla. That means the fight is no longer just over who can etch the smallest transistor; it is also over who can assemble the final machine fastest, closest to the customer, and at the biggest scale. (cnbc.com)
