Igor's Lab lays out TSMC's A13→A12 timeline through 2029, with node milestones and cadence
- Taiwan Semiconductor Manufacturing Co. used its April 22 North America Technology Symposium to extend its leading-edge roadmap to 2029, formally adding A13, A12 and N2U while sharpening how each node targets different chip markets. - The clearest new detail was cadence: A13 is a backward-compatible A14 shrink with 6% area savings for 2029, while A12 adds Super Power Rail backside power delivery for AI and high-performance computing in 2029. - The roadmap also leaves High-NA EUV out through 2029, signaling TSMC plans to stretch existing EUV tools instead of buying ASML’s priciest scanners. (tsmc.com)
Taiwan Semiconductor Manufacturing Co. used its April 22, 2026 technology symposium to map its most advanced chip nodes through 2029, adding A13, A12 and N2U to the public roadmap. (tsmc.com) A chip “node” is the manufacturing generation a design is built on, but the label no longer maps cleanly to a physical measurement in nanometers. TSMC’s new names describe families of process technology, not a single literal transistor size. (igorslab.de) (chipstockinvestor.com) The first concrete addition is A13, which TSMC described as a direct shrink of A14. The company said A13 delivers 6% area savings, keeps full design-rule compatibility with A14, and is scheduled for production in 2029, one year after A14. (tsmc.com) The second is A12, which TSMC previewed as an A14-platform extension with Super Power Rail, its backside power delivery scheme. TSMC said A12 is aimed at artificial intelligence and high-performance computing workloads and is also scheduled for production in 2029. (tsmc.com) (tech.yahoo.com) Backside power delivery moves power wiring to the rear of the chip, leaving more room on the front for signal routing. For large AI accelerators, that addresses current delivery and power integrity limits that simple transistor scaling does not solve on its own. (tech.yahoo.com) (igorslab.de) TSMC also added N2U, a 2028 extension of its 2-nanometer platform. The company said N2U offers 3% to 4% higher speed or 8% to 10% lower power than N2P, with a 1.02x to 1.03x logic-density gain. (tsmc.com) The roadmap now looks more split by end market than by one universal “best” node. Reporting from the symposium said TSMC plans annual client-focused nodes such as N2, N2P, A14 and A13, while heavier AI and high-performance computing nodes such as A16 and A12 arrive on a two-year rhythm. (tech.yahoo.com) That is the point Igor’s Lab emphasized in its April 26 explainer: A13 and A12 are official roadmap entries, but “sub-1nm” production claims for 2029 are still media reports, not equally confirmed product nodes. The site also noted that packaging, thermals and power delivery increasingly shape real chip performance. (igorslab.de) Another notable part of the roadmap is what is missing. Multiple reports from the event said TSMC does not plan to use ASML’s High-NA extreme ultraviolet lithography in volume production through 2029, choosing to keep pushing existing EUV tools instead. (electronicsweekly.com) (tech.yahoo.com) That leaves the 2029 story less about a headline-grabbing “1.2nm” or “1.3nm” label than about how TSMC is spacing upgrades: cheaper migration with A13, heavier power delivery for A12, and a roadmap built around what different chips actually need. (tsmc.com) (igorslab.de)
