Nvidia: AI speeds chip design
Nvidia’s chief scientist described AI tools that are starting to automate many chip‑design tasks, from training LLMs on decades of internal docs to automating cell‑library porting that once took months. He said processes like look‑ahead stage placement and faster verification are compressing design‑to‑tapeout timelines, citing dramatic reductions in manual effort. (x.com)
Nvidia is using artificial intelligence to automate more of the work of designing chips, a shift its chief scientist says is starting to cut manual engineering time. (nvidia.com) Chip design is the process of turning an architecture plan into billions of transistors, then checking that the result works before manufacturing. Nvidia said in 2023 that one chip can take multiple engineering teams as long as two years to build. (blogs.nvidia.com) A large language model in this setting works like a search-and-writing assistant trained on a company’s own engineering history. Nvidia’s ChipNeMo system was trained on internal code, architecture documents and design documents to answer questions, summarize bug reports and write scripts for electronic design automation tools. (eetimes.com) Bill Dally, Nvidia’s chief scientist, introduced ChipNeMo at the International Conference on Computer-Aided Design on October 30, 2023. Nvidia said the model used retrieval-augmented generation, a method that pulls source documents into an answer, to reduce hallucinations and tie responses to internal records. (eetimes.com; blogs.nvidia.com; arxiv.org) Nvidia’s research group says it is now applying artificial intelligence across the chip flow, from register-transfer level design and physical design to verification and sign-off. The group’s public page lists 2024 and 2025 work on large language model-assisted hardware code generation, gate sizing, routing, timing analysis and simulation. (nvidia.com) That matters because verification and physical design have become bottlenecks as Nvidia tries to keep shipping new graphics processing unit, central processing unit and networking chips on a rapid cadence. Nvidia executive Dave Salvator said in August 2024 that these tools were being used to support future products and help maintain the company’s pace of roughly one new graphics processing unit generation per year. (eenewseurope.com) The newer push goes beyond chatbots. Nvidia researchers have been building prediction tools, optimization systems and autonomous agents that can analyze timing reports, optimize cell clusters and generate hardware code with less human hand-holding. (eenewseurope.com; nvidia.com) Some of this work reaches into the smallest building blocks on a chip. In a 2021 paper, Nvidia researchers said their NVCell layout generator could produce layouts with equal or smaller area for more than 90 percent of single-row cells in an advanced-node standard-cell library, showing that automation was already moving into tasks long handled by specialist engineers. (arxiv.org) Verification is also speeding up outside language models. Siemens said on April 9, 2026 that Nvidia and Siemens had captured tens of trillions of pre-silicon verification cycles in a few days using field-programmable gate array-based prototyping, a hardware testing step used before chips are manufactured. (siemens.com) Nvidia’s public line is still productivity, not replacement. In 2023, Dally told EE Times the goal was to make designers more productive, and Nvidia’s own research group describes the effort as improving design quality and design productivity across the flow. (eetimes.com; nvidia.com)
