Siemens Unveils AI for Chip Design

The RTL sign-off that Siemens is targeting is a notorious bottleneck in chip development. This phase ensures the design's structural code is free of critical errors before committing to the costly manufacturing process. Mistakes found after this stage can lead to millions in losses and months of delays. Agentic AI is more than just a pattern-recognition tool; it's a system designed to proactively take steps towards a goal. In this case, the AI doesn't just find potential problems but can generate test plans, assist with documentation, and automate debugging tasks, acting as a tireless digital assistant for human engineers. This move is part of a broader industry-wide race to apply AI to the staggering complexity of modern chips. With design now accounting for over half of the semiconductor industry's R&D costs, companies like Synopsys and Cadence are also developing AI-driven tools to shorten development cycles and improve the chances of first-time-right silicon. The need for such tools is critical, as the industry-wide rate of "first silicon success" has plummeted from 32% in 2020 to just 14% in 2024. Concurrently, the percentage of chip projects running behind schedule has risen to 75%, highlighting a growing verification crisis that automation aims to solve. Siemens EDA, the division behind this technology, is a major player in the electronic design automation market and was formerly known as Mentor Graphics. The company provides a complete suite of tools covering the entire semiconductor design flow, from initial simulation to manufacturing preparation. The new AI capabilities are integrated into the Questa One platform, which unifies previously separate verification tasks like simulation and formal analysis into a single, intelligent system. The platform leverages analytical, predictive, and generative AI to enhance decision-making and reduce manual effort for engineering teams.