Siemens introduces AI for chip design

Siemens' move is part of a broader industry trend where Electronic Design Automation (EDA) is increasingly leveraging AI to manage the skyrocketing complexity of modern chip design. The verification process, ensuring a chip's design is correct before the costly manufacturing stage, has become a major bottleneck, creating a "verification productivity gap" that AI is poised to address. The "agentic AI" in Questa One refers to autonomous software agents capable of reasoning, planning, and executing complex verification tasks with less human intervention. This approach differs from earlier AI that merely assisted engineers, aiming instead for a more self-optimizing and intelligent process. The system is designed to handle advanced designs like 3D-ICs and chiplet-based architectures. Register-transfer level (RTL) is a critical stage in chip design where the flow of digital signals between hardware registers is modeled using a hardware description language like Verilog or VHDL. The "sign-off" is the milestone that confirms the RTL code is structurally sound and ready for the next stages of synthesis and physical implementation. Errors found after this stage are significantly more expensive and time-consuming to fix. Siemens EDA, formerly Mentor Graphics, is one of the "big three" in the EDA industry, alongside Synopsys and Cadence, who together command over 85% of the market. All three are in a race to integrate AI into their toolsets, often collaborating with foundries like TSMC to optimize AI-driven flows for advanced manufacturing processes. Competitors like Synopsys and Cadence have also announced their own AI-powered platforms, such as Synopsys.ai and Cadence.AI.