TSMC tightening from TPU demand
Rising Google TPU orders and demand for advanced‑node capacity are tightening TSMC capacity, which could delay some rival chip programs and indirectly strengthen suppliers with assured node access. Market notes and TSMC coverage this week flagged that capacity pressure as a material supply constraint. (themarketsdaily.com, tickerreport.com)
Supply‑chain trackers say Google trimmed its 2026 TPU production plan from roughly 4.0 million units to about 3.0 million after advanced CoWoS packaging slots tightened. (moomoo.com) Multiple reports show Google is splitting TPU work across Broadcom and MediaTek for the v7/v7e cycle, with TrendForce and Economic Daily News citing MediaTek securing initial CoWoS allocations (reported near ~10,000 wafers annually). (trendforce.com) A Morgan Stanley‑tracked supply model projects NVIDIA will absorb the lion’s share of CoWoS demand—roughly 595,000 wafers (about 60% of 2026 capacity), leaving materially less advanced packaging headroom for other ASIC programs. (semimedia.cc) TSMC has publicly signaled a stepped expansion of CoWoS throughput and is preparing to route portions of its advanced packaging work to OSAT partners to hit industry forecasts of ~100k–150k CoWoS wafers per month by late‑2026. (particle.news) Analyst tallies and conference call notes put realistic TPU output for 2026 in the low‑millions (3.1–3.2M in several supply‑chain checks), with full external‑sales scale for Google now more likely in 2027 once packaging ramps complete. (nand-research.com) Market coverage flags that firms with embedded foundry/packaging relationships—Broadcom, MediaTek and large OSATs such as ASE—stand to gain relative leverage because secured CoWoS allocations shorten time‑to‑market for their customers’ ASIC builds. (trendforce.com)
