Siemens Deploys AI for Chip Design

The move to agentic AI is a direct response to the "verification productivity gap," a long-standing issue where the complexity of chip designs grows faster than the ability of engineers to test them. Functional verification can consume up to 70% of a design team's time and resources, creating a significant bottleneck in getting new chips to market. Siemens' strategy, articulated by executives like Mike Ellow, CEO of Siemens EDA, involves integrating AI across the entire design portfolio. This isn't a recent pivot; the company has been developing a broad AI platform for years with a team of 1,400 AI experts and nearly 4,000 related patents, ensuring the technology is built on a proven, industrial-grade foundation before being applied to specific EDA tools. The Questa One Agentic Toolkit features five specific AI agents, including an RTL Code Agent for generating code, a Lint Agent for error checking, and a Debug Agent for failure analysis. According to Abhi Kolpekwar, Siemens EDA's VP and General Manager of Digital Verification Technologies, this transforms verification from a reactive process into an intelligent, self-optimizing system. Early adopters are reporting significant and immediate productivity gains. Microsoft, for instance, noted that parts of the Questa One solution slashed their verification time from weeks to days. Akshay Aggarwal, a senior engineering director at MediaTek, stated that his engineers became proficient with the new toolkit within hours, highlighting a rapid learning curve. Underpinning this new AI capability is a significant partnership with NVIDIA. Siemens is integrating NVIDIA NIM and Nemotron reasoning models to power the AI-driven workflows, a collaboration both companies are expanding to create what they term an "Industrial AI Operating System." The AI works by automating and accelerating key steps in the RTL sign-off process, a critical phase where bugs become exponentially more expensive and time-consuming to fix. Traditional methods are often plagued by "noisy" and voluminous violation reports and difficulties in checking the connectivity between different design blocks—challenges the new AI agents are designed to resolve automatically. This is part of a broader industry shift from simple AI assistance to "agentic" systems that can reason, plan, and execute complex tasks autonomously. The goal is to free up experienced engineers from routine, manual processes to focus on more innovative aspects of chip architecture and design. The platform itself, Questa One, was officially unveiled in mid-2025 and represents a significant rewrite of previous tools to unify simulation, formal analysis, and verification IP into a single, data-driven system. For some complex open-source designs, this unified approach has been shown to reduce processing times from over 24 hours to less than a minute.