AMI models integrate equalization for SI

- Cadence spotlighted a Sigrity workflow on April 24 that folds IBIS-AMI equalization models directly into serial-link channel simulation for pre-silicon SI analysis. - The useful detail is what moves into the model: TX/RX equalizers like CTLE, FFE, DFE, plus clock recovery and adaptive behavior. - That matters because 100G-plus SerDes links now need earlier margin prediction before boards, packages, and chiplets get too expensive to fix.

High-speed serial links are now running into a blunt physical problem — the channel is ugly before the silicon even ships. Packages are denser, traces are lossier, chiplets add more discontinuities, and links like PCIe and USB keep pushing data rates up. The news here is that Cadence spent April highlighting a Sigrity flow that uses IBIS-AMI models to pull equalization behavior into signal-integrity simulation much earlier, so engineers can judge whether a link will actually open an eye before tapeout. (semiengineering.com) ### What is an AMI model, really? IBIS-AMI is the industry-standard way to describe the algorithmic part of a SerDes transmitter or receiver without handing over the vendor’s full internal design. The analog channel stays in the simulator as buffers, terminations, packages, vias, connectors, and traces. The AMI part adds the DSP-like behavi(semiengineering.com) under the IBIS Open Forum, which now manages IBIS 8.0 and the AMI framework used across EDA tools. (ibis.org) ### Why wasn’t the old flow enough? Because a raw channel response is no longer the whole story. At modern SerDes speeds, the receiver often survives only because equalization is doing heavy lifting. A plain analog simulation can tell you the channel is lossy, but it can miss the real system question — whether CTLE, FFE, DFE, and clock recovery can rescue the signal well enough to hit margin. MathWorks’ IBIS-AMI documentation(ibis.org)the analog path is treated as linear and time-invariant, while the algorithmic model handles equalization behavior on top. (mathworks.com) ### What changed in this workflow? The practical shift is that equalization is no longer treated like a hand-wavy afterthought. Cadence’s writeup centers on embedding AMI-based TX and RX behavior directly into channel simulation so engineers can inspect eye diagrams, BER trends, and timing margins with the equalizers in the loop. That means pre-sili(mathworks.com)ter pre-emphasis and receiver equalization actually closes the design?” (semiengineering.com) ### Which equalizers are we talking about? The usual cast: FFE on the transmit side, CTLE and DFE on the receive side, plus clock and data recovery. Those are the knobs that compensate for inter-symbol interference and channel loss. IBIS-AMI flows can model both statistical eyes and bit-by-bit time-domain behavior, which matters because som(semiengineering.com) processes an actual bit stream. (mathworks.com) ### Why do eye diagrams and BER both matter? An eye diagram gives the fast visual answer — how much voltage and timing margin is left at the sampling point. BER tells you whether that margin survives at the error rates the standard actually cares about. In AMI-based flows, waveform processing can be turned into eye density, bathtub curves, and BER-o(mathworks.com), but from burst-error behavior and feedback effects inside DFE loops. (cadence.com) ### Why is this getting more important now? Because links beyond 100 Gb/s are forcing more equalization into both analog and digital domains. IBIS Summit material on ADC-based SerDes says data rates are still climbing, PAM4 increases equalization demands, and(cadence.com)come part of the SI problem. (ibis.org) ### So who benefits? Chip vendors, package teams, board designers, and system integrators all do. AMI models let a SerDes supplier share realistic behavior with customers without exposing the full internal implementation. That decouples the model from the simulator and gives downstream teams a way to validate complete links earlier. Texas Instruments’ AM64x documentation uses exactly that framing —(ibis.org)m-level high-speed links across EDA environments. (ibis.org) ### What’s the bottom line? The point is not that AMI is new. The point is that equalization has become too central to leave outside the main SI loop. As serial links get faster and packaging gets messier, pre-silicon signal integrity increasingly means simulating the channel and the recovery algorithms together — or finding out too late that the link only looked healthy on paper. (semiengineering([ibis.org)al-link-signal-integrity-with-ami-model/))

Get your own daily briefing

Scout delivers personalized news, insights, and conversations tailored to your role and industry.

Download on the App Store

Shared from Scout - Be the smartest in the room.