US–Japan packaging R&D consortium
- A US–Japan consortium led by Resonac launched a Silicon Valley R&D collaboration for next‑gen packaging. (x.com) - The initiative reportedly gathers twelve firms to work on materials, equipment and packaging research. (x.com) - The collaboration creates new cross‑discipline integration and verification demands for firms working between design and downstream partners. (x.com)
A U.S.-Japanese chip-packaging consortium led by Resonac opened a Silicon Valley research center on April 20 to speed development of next-generation semiconductor assembly. (resonac.com) The group, called US-JOINT, now has 12 members from Japan and the United States and began full-scale operations in Union City, California, in April 2026. ULVAC listed the members as Resonac, 3M, KLA, Kulicke and Soffa, TOPPAN, Tokyo Ohka Kogyo, TOWA, Namics, MEC, Moses Lake Industries, Azimuth Industrial and ULVAC. (ulvac.co.jp) Chip packaging is the back-end step that turns a finished silicon die into a usable product by connecting it, protecting it and managing heat and power. Resonac said the new site is the first in the United States dedicated to advanced semiconductor-packaging technologies. (resonac.com) The center is set up to test new package ideas with major chip users in Silicon Valley instead of sending designs through a slower chain of materials suppliers, tool makers and offshore assembly lines. ULVAC said limited opportunities for fast, practical validation had become a bottleneck as new packaging concepts multiplied. (ulvac.co.jp) That bottleneck has grown as artificial intelligence and autonomous-driving chips demand denser connections and more complex stacks, including 2.5D and 3D packaging. Resonac said those designs are being pushed by large semiconductor companies and fabless chip designers in Silicon Valley. (semiconductor-digest.com) Resonac said the goal is to cut proof-of-concept work from about six months to as little as one month by putting 12 companies and key customers around one development base. Broadcom Vice President Dilip Vijay said in Resonac’s release that the industry had needed this kind of collaborative effort. (resonac.com) The project also shows how packaging has moved closer to the center of chip competition in the United States. Resonac said US-JOINT expands its earlier JOINT and JOINT2 programs in Japan, which were built to connect materials and equipment suppliers across company lines. (semiconductor-digest.com) At the Union City site, the consortium said it has cleanrooms rated Class 100 and 1,000 plus tools for patterning, bonding, molding, plating, evaluation and analysis. Those are the practical pieces needed to see whether a package design can survive real manufacturing, not just a computer model. (ulvac.co.jp) The opening ceremony brought in government officials and company representatives from both countries, underscoring how chip policy now reaches past wafer fabrication into assembly and integration. For Resonac and its partners, the next test is whether a Silicon Valley packaging hub can turn customer requests into manufacturable designs faster than the old handoff model. (resonac.com)
