TSMC details 3nm capacity roadmap
- Taiwan Semiconductor Manufacturing Co. used its April 22 North America Technology Symposium to map bigger 3-nanometer output and much larger AI chip packages. - TrendForce said TSMC’s Taiwan 3nm capacity is now projected to hit 180,000 wafers a month by end-2026, up from 150,000 previously. - The roadmap shifts scaling toward packaging, with CoWoS growing from 5.5 reticles now to 14 in 2028 and beyond. (trendforce.com)
A chip “node” is the manufacturing recipe for transistors, while packaging is the way multiple chips and memory are wired into one module. TSMC is now expanding both at once, with 3-nanometer output rising and CoWoS packages getting much larger for artificial-intelligence systems. (trendforce.com 1) (trendforce.com 2) At TSMC’s North America Technology Symposium in Santa Clara on April 22, the company said its current CoWoS production is at 5.5 reticles, a measure of how large a stitched package can be on silicon. It said 14-reticle CoWoS is planned for 2028, with packages beyond 14 reticles in 2029. (tsmc.com) (pr.tsmc.com) TSMC said a 14-reticle CoWoS package can integrate about 10 large compute dies and 20 high-bandwidth-memory stacks. Taipei Times reported the company paired that roadmap with a 40-reticle System-on-Wafer-X target for 2029. (pr.tsmc.com) (taipeitimes.com) TrendForce reported Monday that TSMC’s Taiwan-based 3nm fabs are now projected to reach 180,000 wafers a month by the end of 2026, versus an earlier 150,000-wafer expectation. It said monthly output was around 120,000 to 130,000 wafers at the end of 2025. (trendforce.com) That 3nm ramp is being pulled by AI accelerators, graphics processors and server chips rather than phones alone. TrendForce said demand from Nvidia, Advanced Micro Devices, Intel and automotive customers is still absorbing available 3nm capacity. (trendforce.com) The packaging side explains why. CoWoS, short for chip-on-wafer-on-substrate, lets TSMC place logic dies and high-bandwidth memory side by side on a shared interposer, like turning separate chips into one tightly connected board. (trendforce.com) (eetimes.com) EE Times reported TSMC executives and analysts framed those larger packages as a new source of density gains, with system integration adding performance even when transistor shrinks get harder and more expensive. The same report said TSMC is still avoiding ASML’s high-numerical-aperture extreme-ultraviolet tools for A14 and A13. (eetimes.com) TrendForce said a single CoWoS wafer now sells for about $10,000, roughly on par with 7nm wafers, and advanced packaging contributed about 10% of TSMC revenue in 2025. It said investors expect CoWoS capacity to reach about 1.3 million units in 2026 and 2 million in 2027. (trendforce.com) TSMC also used the symposium to push its process roadmap out to 2029. The company said A13 and A12 are both scheduled for production in 2029, while N2U, a tuned version of its 2-nanometer platform, is scheduled for 2028. (pr.tsmc.com) (eetimes.com) The result is a roadmap where the factory line and the package substrate both become bottlenecks. TSMC is not just making smaller chips; it is reserving more of the performance gain for the way those chips and memory are assembled into one system. (trendforce.com 1) (trendforce.com 2)
