Arteris Tech Tapped by NXP for Edge AI
NXP is expanding its use of Arteris Technology's data movement fabrics to boost its leadership in edge AI. The deal focuses on advanced interconnect IP for NXP's next-gen chips targeting automotive, industrial, and consumer applications, aiming to improve data flow for complex AI workloads.
NXP's expanded use of Arteris IP isn't just about a single product; it involves a suite of technologies including FlexNoC and Ncore network-on-chip (NoC) IP, alongside CodaCache last-level cache IP. This combination is crucial for managing the complex, high-performance data movement required in the latest AI-driven system-on-chip (SoC) designs for vehicles, industry, and consumer devices. The core challenge in advanced AI chips is not just processing power, but efficient data flow between CPUs, neural processing units (NPUs), and memory. Arteris' NoC technology acts as the data highway on the chip, aiming to reduce latency and power consumption while maximizing bandwidth, which is critical for the massive parallelism demanded by AI workloads. As of early 2026, Arteris' technology has been deployed in over 4 billion chips and chiplets. This deal supports NXP's broader strategy for a software-defined, secure edge. Their S32G family of vehicle network processors, for instance, already integrates high-performance processing with ASIL D functional safety and hardware security. Incorporating Arteris' advanced interconnects will help offload data movement tasks from the main processors in next-generation chips. NXP is also investing heavily in the software side with its eIQ AI Toolkit and a new eIQ Agentic AI Framework, announced in January 2026. These tools are designed to simplify the deployment of AI models on resource-constrained edge devices, addressing challenges like limited memory and the need for real-time, deterministic decision-making without cloud reliance. The move is part of an industry trend to handle more AI processing locally on devices for reasons of latency, privacy, and efficiency. NXP's strategy involves integrating dedicated NPUs to accelerate AI inference by orders of magnitude compared to a standard CPU, making complex AI viable in power-sensitive and battery-powered applications.
