Intel bets on packaging to close gaps

The chip shortage in artificial intelligence is no longer just about making the silicon. It is also about packaging it, which is the step where several chips and stacks of high-bandwidth memory get wired together into one finished part. (intel.com) That packaging step has become a choke point because modern artificial intelligence chips are too big and too power-hungry to stay as one slab of silicon. Companies now split them into smaller pieces and reconnect them inside one package, like building one engine from several machined parts. (intel.com) Taiwan Semiconductor Manufacturing Company’s best-known answer is called Chip on Wafer on Substrate, which mounts logic chips and memory on a large silicon base so they can talk at very high speed. Taiwan Semiconductor Manufacturing Company says this platform is built for artificial intelligence and high-performance computing, where bandwidth and integration density are the whole game. (tsmc.com) The problem is that even Taiwan Semiconductor Manufacturing Company has struggled to add enough of that packaging fast enough for the artificial intelligence boom. The company says Chip on Wafer on Substrate capacity has been growing at more than 50% a year from 2022 to 2026, which tells you how hard customers have been pushing on the narrowest part of the supply chain. (trendforce.com) (tsmc.com) Intel is trying to attack that bottleneck with a different tool called Embedded Multi-die Interconnect Bridge. Instead of laying every chip on one giant silicon plate, Intel embeds small silicon bridges inside the package substrate so separate chips can connect where they actually need to connect. (intel.com) Intel’s new version is called Embedded Multi-die Interconnect Bridge-T, and the “T” means through-silicon vias, which are tiny vertical holes through the bridge that add more routing options. Intel says Embedded Multi-die Interconnect Bridge-T is aimed at logic-to-memory designs and can simplify assembly while easing reuse of parts from other package designs. (intel.com) This week’s news is that Intel says Embedded Multi-die Interconnect Bridge-T is moving into fab rollout in 2026. Intel also says the technology can support package sizes above 6 times the reticle limit today, above 8 times the reticle limit this year, and above 12 times by 2028, which is exactly the kind of scale large artificial intelligence accelerators need. (tomshardware.com) (intel.com) That is why investors suddenly care about a part of chipmaking that used to sound like factory plumbing. Intel’s market value moved above $300 billion this week for the first time in about 25 years as analysts started pricing in stronger prospects in personal computer chips, artificial intelligence silicon, and foundry packaging work. (tomshardware.com) (techspot.com) There is also a customer angle behind the stock move. Reports this week said Intel has been in talks with Amazon and Google about advanced packaging services for custom artificial intelligence chips, which would turn packaging from an internal Intel capability into a foundry product other companies buy. (msn.com) (trendforce.com) Intel is not replacing Taiwan Semiconductor Manufacturing Company at the leading edge of chip fabrication with this move. Intel is betting that if the hardest thing to buy in artificial intelligence is the finished package, then owning one of the few credible ways to build that package can close a gap that raw transistor leadership alone no longer decides. (cnbc.com) (intel.com)