FPGAs still central to HFT
Ex‑trader reporting and social threads highlight continued institutional usage of 'ultra low latency FPGA technology' for market‑making across venues — underlining that hardware acceleration remains a proprietary edge for firms, not retail reported. The takeaway: microsecond advantages from FPGAs and custom NICs are still being fielded as active competitive differentiators in production.
Citadel Securities currently lists dedicated FPGA Engineer openings across New York, London, Hong Kong and Singapore [job posting] (citadelsecurities.com), and industry recruitment boards show senior FPGA roles for trading paying roughly $200k–$700k, underlining sustained headcount and cash investment by institutions [job ad] (efinancialcareers.com). Major vendor M&A has folded FPGA networking IP into enterprise stacks — Cisco acquired Exablaze for low‑latency FPGA NICs and Layer‑1 switching in early 2020 [acquisition] (cisco.com), Xilinx bought Solarflare in April 2019 for its NIC and Onload tech [announcement] (prnewswire.com), and AMD completed the Xilinx acquisition on Feb 14, 2022 [press release] (ir.amd.com). Hardware launches continue: recent product coverage highlights AMD’s Solarflare X4/NS9480 SmartNICs targeted at low‑latency trading workloads [product launch] (servethehome.com), while ExaBlaze’s ExaNIC FPGA NICs remain documented in public repos and were integrated into Cisco’s Nexus low‑latency portfolio [ExaNIC docs] (github.com). Market‑data vendors are consolidating FPGA capabilities — Exegy announced acquisition of FPGA specialist NovaSparks on Jan 14, 2026 to combine FPGA market‑data normalization with Exegy’s managed platforms and “nanosecond” performance claims [acquisition press release] (prnewswire.com). Kernel‑bypass stacks and their measured gains are still being productionized: Solarflare/OpenOnload‑based tests show single‑digit microsecond UDP/TCP application latencies on 10GbE setups [whitepaper] (arista.com), and recent industry guides list DPDK, RDMA and Onload as standard techniques for achieving single‑digit or sub‑microsecond paths from NIC to application in trading stacks [technical guide] (quantvps.com). Public research and open‑source tick‑to‑trade FPGA projects demonstrate sub‑microsecond pipelines: academic implementations describe FAST‑protocol FPGA decoders and hardware market‑data parsers [paper] (people.ucsc.edu), and community repos claim end‑to‑end FPGA systems achieving sub‑microsecond ingress‑to‑decision latencies in demonstration builds [open source] (github.com).
