Siemens Deploys AI for Chip Design
Siemens announced it is accelerating integrated circuit design and verification using agentic AI in its Questa One platform. The new AI-driven workflows are designed to speed up the register-transfer level (RTL) sign-off process. The system combines AI agents with configurable human expertise.
The use of "agentic AI" in Electronic Design Automation (EDA) marks a shift from assistive automation to autonomous, goal-driven software agents. These agents can independently reason, learn, and execute complex chip design tasks that traditionally required significant human intervention. Siemens' move is part of a broader industry trend. Globally, leading semiconductor companies are projected to spend over $500 million on AI design tools in 2026. Competitors like Synopsys have also been developing AI-driven tools, such as DSO.ai, which has been shown to reduce chip design timelines from months to weeks. The focus on the register-transfer level (RTL) is strategic, embodying the "shift left" principle in chip design. Identifying and fixing bugs at this early stage is far more efficient and less costly than making changes after the design has progressed to the netlist or physical layout stages. The Questa One platform, launched by Siemens EDA around June 2025, is engineered to address the growing complexity of modern System-on-Chip (SoC) and 3D-IC designs. It integrates various verification technologies into a single system, from simulation and formal verification to hardware-assisted emulation. Siemens claims significant performance gains with Questa One, including up to 50 times faster coverage closure and 8 times faster gate-level simulation when integrated with its Tessent software. The platform is designed to unify workflows and manage the massive amounts of data generated during the verification of complex chips.
