TSMC defends capacity allocation
TSMC chairman C.C. Wei denied customer‑favoritism claims amid tight advanced‑node capacity in Q1 2026 while signalling continued strong demand for advanced processes into Q2. The company and market commentators say advanced‑node capacity remains constrained as AI chip demand continues to push utilisation. (digitimes.com)
Taiwan Semiconductor Manufacturing Co. said on April 16 that it is not favoring any one customer as demand keeps its most advanced chipmaking lines tight. (digitimes.com) Chairman and chief executive C.C. Wei made the point on TSMC’s first-quarter 2026 earnings call, where the company also guided second-quarter revenue to $39.0 billion to $40.2 billion, up from $35.90 billion in the first quarter. (investor.tsmc.com, investor.tsmc.com) TSMC said first-quarter revenue rose 35.1% from a year earlier to NT$1.134 trillion, and March revenue alone climbed 45.2% year over year to NT$415.19 billion. (pr.tsmc.com) The bottleneck is at the leading edge, where smaller process nodes such as 3-nanometer and 2-nanometer are used for high-performance chips in artificial intelligence servers and premium smartphones. TSMC told investors it is increasing 3-nanometer capacity and has started 2-nanometer mass production. (investor.tsmc.com, digitimes.com) TSMC’s own guidance points to the squeeze continuing into June. The company said second-quarter gross margin should be 65.5% to 67.5%, with demand supported by its “industry-leading” advanced technologies. (investor.tsmc.com, investor.tsmc.com) That matters because TSMC is the main contract manufacturer for many of the world’s biggest chip designers, and a shortage at its newest nodes can slow product launches across data centers, phones and cars. TSMC said it produced more than 17 million 12-inch-equivalent wafers in 2025 and served about 465 customers. (tsmc.com, investor.tsmc.com) Market reports have pointed to Nvidia and other artificial-intelligence chip designers absorbing a large share of advanced production and advanced packaging, especially CoWoS, the chip-stacking technology used to connect processors to high-bandwidth memory. Digitimes reported in late March that 3-nanometer capacity remained constrained at the end of the first quarter. (digitimes.com, digitimes.com) Wei’s denial is aimed at that backdrop: customers want reassurance that scarce wafer starts are being allocated by commercial and production planning, not by favoritism. TSMC has not published a customer-by-customer capacity breakdown. (digitimes.com, investor.tsmc.com) For now, TSMC’s message is that demand is still outrunning supply at the top end, and the company is spending to add more room rather than signaling any letup in artificial-intelligence orders. (investor.tsmc.com, digitimes.com)
