TSMC expands; Cadence deepens ties
- Taiwan Semiconductor Manufacturing Co. said it plans to open an advanced chip-packaging plant in Arizona by 2029, adding a key back-end step now concentrated in Taiwan to its U.S. manufacturing buildout. - Cadence expanded ties with TSMC on certified design flows for N3, N2, A16 and A14, after separate April 15 deals with Nvidia and Google around agentic AI tools. - Advanced packaging has become an AI-chip bottleneck, so adding U.S. capacity and more preapproved design flows could shorten delivery and validation cycles. (reuters.com)
Modern AI chips are often several pieces of silicon stitched together, and TSMC now plans to bring more of that stitching work to Arizona by 2029. (reuters.com) Taiwan Semiconductor Manufacturing Co. executive Kevin Zhang told Reuters on April 22 that the company plans to open a chip-packaging plant in Arizona by 2029. Reuters said the site would handle advanced packaging used to join multiple chiplets into one processor package. (reuters.com) Reuters reported the Arizona operation is aimed at technologies such as Chip-on-Wafer-on-Substrate, or CoWoS, and 3D integrated circuits, two methods used heavily in AI processors. Those steps have become a supply bottleneck for Nvidia and other chip designers because packaging capacity has lagged wafer production. (reuters.com) TSMC’s U.S. expansion has focused mostly on front-end wafer fabrication until now. In March 2025, the company said it would raise planned U.S. investment to $165 billion, including three new fabs, two advanced packaging facilities and a research-and-development center in Arizona. (tsmc.com) That makes the April 2026 packaging target more concrete than the earlier blueprint. A local packaging step could reduce the need to ship partly finished chips back to Taiwan for final assembly before they go to U.S. customers such as Nvidia and Apple. (reuters.com) (tsmc.com) Cadence is moving on the design side of the same problem. On April 22, Cadence said it expanded its long-running partnership with TSMC to deliver IP, signoff-ready infrastructure and certified flows for TSMC’s N3, N2, A16 and A14 process technologies. (cadence.com) Cadence said those TSMC-certified digital, custom and analog, 3D-integrated-circuit and signoff platforms are meant to cut design iterations and speed time to tapeout, the point when a chip design is sent for manufacturing. The company also said it is developing “agent-ready” flows that use agentic AI to optimize power, performance and area. (cadence.com) A week earlier, at CadenceLIVE Silicon Valley on April 15-16, Cadence announced two more alliances. One expanded work with Nvidia on agentic AI, physics-based simulation and digital twins; the other paired Cadence’s ChipStack AI Super Agent with Google’s Gemini models on Google Cloud. (cadence.com 1) (cadence.com 2) (events.cadence.com) Cadence said the Google Cloud setup is available now on Google Cloud Marketplace as a “click-to-deploy” service for chip design and verification. In the Nvidia tie-up, Jensen Huang said CUDA-accelerated computing and AI are “reinventing the engineering process,” according to Cadence’s release. (cadence.com 1) (cadence.com 2) Taken together, the announcements show two choke points in the AI-chip pipeline: too little advanced packaging capacity and too much design work before a chip is ready for fab. TSMC is adding physical capacity in Arizona, while Cadence is trying to remove some of the waiting on the software side before those chips hit the line. (reuters.com) (cadence.com)
