Google–Marvell Chip Talks

Google is discussing new artificial intelligence chips with Marvell that would be built to run models after training, not to train them. (theinformation.com) The Information reported on April 19 that Google and Marvell are discussing two chips for inference, including a memory processing unit designed to work alongside Google’s Tensor Processing Unit, or TPU. (theinformation.com) A TPU is Google’s in-house application-specific integrated circuit, or ASIC, a chip built for one job rather than many. Google says its current TPU line is designed for both training and inference, and its Ironwood generation is aimed at large-scale model serving. (cloud.google.com, cloud.google.com) Inference is the part of artificial intelligence that answers a prompt, ranks a search result or generates a reply after a model has already been trained. That workload has become a bigger business as companies move from building models to serving them at scale. (cloud.google.com, professional.content.cirrus.bloomberg.com) Marvell has been pitching itself as a supplier for that shift. At its 2025 custom artificial intelligence investor event, the company said demand for custom silicon was spreading across more customers, more chip types and more networking and packaging technologies. (marvell.com, marvell.com) Bloomberg Intelligence said in January that the overall AI accelerator market could reach $604 billion by 2033, while custom ASICs are projected to grow faster than the broader market. Bloomberg’s release also said Broadcom and Marvell are among the companies positioned to benefit from that adoption. (bloomberg.com) That forecast fits a wider move by cloud companies to build more of their own chips instead of buying only off-the-shelf accelerators. CNBC reported in November that Google, Amazon, Meta, Microsoft and OpenAI were all pursuing custom AI silicon as alternatives gained ground beside Nvidia’s graphics processors. (cnbc.com) Google has been on that path for years. Its cloud unit says TPUs are purpose-built for neural networks, and the company has kept updating them as it tries to turn internal chip design into a cloud advantage. (cloud.google.com, cnbc.com) Marvell, for its part, has been expanding the pieces it can sell around a custom accelerator, from packaging to interconnects to co-packaged optics. The company said in 2025 that its multi-die packaging platform could support accelerator designs 2.8 times larger than conventional single-die implementations. (investor.marvell.com, investor.marvell.com) The talks are still talks, and neither company has publicly announced a deal. But if they turn into products, they would add another customer-specific chip program to a market that is moving from general-purpose graphics processors toward more specialized silicon. (theinformation.com, marvell.com)