TSMC 3nm Capacity Tight
TSMC’s 3nm capacity is the most constrained part of the AI chip supply chain heading into Q2 2026 — customers are seeing limited availability and rationing as cloud AI demand soaks up fabs. That bottleneck raises immediate risks for any Apple Silicon ramps that rely on advanced nodes and forces Fremont teams to prioritize yield recovery and contingency sourcing. (digitimes.com)
Microsoft’s Maia 200 inference accelerator is confirmed by Microsoft to be fabricated on TSMC’s 3nm process and ships with a reengineered memory subsystem that includes ~216GB of HBM3e, directly consuming N3 wafer and HBM capacity. (blogs.microsoft.com) Broadcom told reporters that TSMC is “hitting (production capacity) limits” and that capacity expansion through 2027 has already become a bottleneck for the supply chain in 2026. (money.usnews.com) TSMC CEO C.C. Wei warned at the Semiconductor Industry Association awards that the company’s advanced‑node capacity is “about three times short” of major customers’ planned consumption. (tomshardware.com) Independent trackers and industry analyses report N3 lead times stretching beyond 50 weeks and industry bookings that effectively allocate 3nm capacity 18–24 months forward for high‑volume customers. (siliconanalysts.com) Bloomberg data show TSMC shifting more output to high‑performance AI and datacenter customers, with January–February 2026 revenue growth of roughly 30% as Nvidia/AI work dominated wafer allocation. (bloomberg.com) Advanced packaging and memory are compounding the bottleneck: CoWoS packaging demand and HBM3e purchases tied to hyperscaler ASICs are creating parallel shortages that constrain the usable 3nm output. (siliconanalysts.com) Apple has been reported to hold large allocations across advanced nodes and is concurrently expanding its American Manufacturing Program with new U.S. partners as part of broader contingency and on‑shore sourcing plans. (technode.com)
