Arasan Debuts Combo Memory IP
Arasan has released the industry's first xSPI NOR and eMMC NAND Combo PHY IP. This integrated solution aims to simplify the design of embedded systems that require both types of non-volatile memory.
This combo IP targets mission-critical applications in the aerospace, defense, and medical sectors that demand both the high reliability of NOR flash for boot code and the cost-effective bulk storage of NAND flash. The design leverages a shared I/O and analog front-end architecture, a key feature that significantly reduces pin count and silicon footprint on System-on-Chip (SoC) and microcontroller (MCU) platforms. The physical layer (PHY) IP is compliant with both the JEDEC JESD251 standard for xSPI and the eMMC 5.1 standard. It enables maximum data transfer speeds of 400 MB/s in both xSPI and eMMC HS400 modes, facilitating faster boot times and efficient data logging. Founded in 1995, Arasan Chip Systems has a history of providing IP for mobile storage and connectivity, with over a billion chips shipped containing their IP. The company has licensed its eMMC IP over 200 times and positions itself as a leading provider of xSPI IP. The xSPI + eMMC Combo PHY IP is available for immediate licensing and can be implemented on leading foundry process nodes ranging from 28nm to 3nm. Arasan delivers this as a "Total IP Solution," which includes the digital IP, the analog mixed-signal PHY, verification IP, software stacks, and hardware development kits (HDKs) to aid in integration and compliance testing. The JEDEC xSPI standard itself is a crucial development as it unifies the previously fragmented high-speed NOR flash market, creating a common protocol for manufacturers and simplifying the design process for engineers. In parallel, eMMC integrates a NAND flash controller on the same die, offloading low-level flash management from the host CPU.
