Siemens Deploys Agentic AI for Chip Design Verification

Siemens has integrated agentic AI into its Questa One verification platform to accelerate integrated circuit design. The AI-driven workflows are domain-scoped and aim to speed up the register-transfer level (RTL) sign-off process. The new functionality is designed to integrate with existing customer investments to optimize performance.

Siemens is embedding agentic AI into its Electronic Design Automation (EDA) tools to tackle the verification bottleneck, a phase that consumes over 60% of the chip design cycle. This move pits them directly against rivals like Cadence with its Cerebrus and JedAI platforms, and Synopsys with its DSO.ai and VSO.ai tools, all of whom are in a race to automate chip design with AI. The goal is to shift from AI-assisted tools to fully autonomous, goal-driven agents that manage complex workflows like RTL sign-off. The register-transfer level (RTL) sign-off is a critical and often painful step where design flaws can cause costly delays. Traditionally, engineers manually run lint checks, clock domain crossing (CDC) analysis, and formal verification, a process that becomes unwieldy with system-on-chip (SoC) designs exceeding 100 million gates. Siemens' AI agents aim to automate test plan generation, regression testing, and debugging, allowing engineers to focus on higher-value tasks. This push into AI-driven verification is a direct response to the exploding custom silicon market. Hyperscalers like Google (TPU), Amazon (Trainium, Inferentia), Microsoft (Maia), and Meta (MTIA) are designing their own chips to optimize for specific AI workloads, creating massive demand for EDA tools that can accelerate these complex designs. The success rate for getting designs right on the first try (first silicon success) has plummeted from 32% in 2020 to just 14% in 2024, highlighting the urgent need for smarter verification. For GTM teams, the narrative shifts from selling individual tools to selling a platform-level AI strategy that delivers productivity gains and faster time-to-market. The key value proposition is enabling customers, from AI startups to hyperscalers, to de-risk their multi-million dollar tape-outs. This requires a deep understanding of the customer's design challenges, whether it's optimizing for power, performance, and area (PPA) or ensuring robust verification for a complex multi-die system. The Siemens Questa One Agentic Toolkit initially features five distinct AI agents and is designed to integrate with external platforms like GitHub Copilot and Claude. This open approach contrasts with more closed ecosystems and acknowledges that engineering workflows are becoming increasingly complex and reliant on multiple tools. The long-term vision for the EDA industry is a move toward L4 autonomous chip design, where AI agents can manage the entire flow, from architectural definition to the final GDSII layout files.

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