Siemens Deploys Agentic AI for Chip Design

The Siemens Questa One Agentic Toolkit is powered by five distinct AI agents designed to tackle specific, time-consuming tasks within the chip verification process. These include an RTL Code Agent for generating synthesizable code, a Lint Agent for checking design errors, a CDC Agent for clock domain crossing verification, a Verification Planning Agent that automates the creation of verification plans, and a Debug Agent to speed up failure analysis. Underpinning this toolkit are large language models from NVIDIA, specifically the Nemotron family, which are accessed via NVIDIA NIM microservices. This collaboration provides the advanced reasoning and code generation capabilities necessary for the agents to understand the design, its specifications, and the verification context in real-time. The system is designed to be platform-agnostic, integrating with existing tools like GitHub Copilot and other IDEs. One of the most critical and error-prone aspects of System-on-a-Chip (SoC) design is ensuring data transfers correctly between dozens or even hundreds of different clock domains. Failures in Clock Domain Crossing (CDC) can lead to metastability and data corruption that are difficult to detect with traditional simulation. The dedicated CDC Agent automates the verification of these crossings, aiming to eliminate a major source of bugs that could otherwise require a costly chip re-spin. The workflow mirrors a human verification engineer's process but at a much faster pace. For instance, the Verification Planning Agent can analyze a design specification written in natural language and automatically generate a structured verification plan for an engineer to review and approve. Similarly, in formal verification, AI agents can now automatically generate SystemVerilog Assertions (SVAs) from specifications, set up the verification environment, and even provide initial analysis on failures, a process that was previously heavily manual and reliant on expert knowledge. Early adopters are reporting significant productivity gains. Engineers at MediaTek, a major designer of SoCs for consumer electronics, were able to complete tasks in hours that typically take days and master workflows that would normally require weeks of training. Specifically, they noted that generative AI features for formal verification saved "weeks of engineering time," while AI-driven regression testing saved "days of regression and debugging time." This shift towards agentic AI alters the role of the verification engineer, moving them from manual task execution to reviewing and guiding the output of AI agents. The goal is to automate the repetitive and tedious aspects of verification, freeing up engineers to focus on more complex system-level design and validation challenges. This allows smaller teams to manage the increasing complexity of modern chip designs and improve the rate of first-pass silicon success.