Siemens Deploys Agentic AI for Chip Design

The verification stage for modern systems-on-a-chip (SoCs) has become a critical bottleneck, often consuming the majority of a project's resources and time. As chip designs escalate to billions of transistors on advanced 3nm and 5nm nodes, the complexity of ensuring design correctness before manufacturing is a primary constraint on time-to-market. The register-transfer level (RTL) sign-off is a crucial step where bugs must be caught, as errors discovered after this stage can lead to costly and time-consuming fixes. Issues like unintended latches, incorrect handling of clock domain crossings (CDC), and reset glitches are common mistakes that can cause functional bugs or even require a complete chip respin if they make it to silicon. Agentic AI in Electronic Design Automation (EDA) represents a shift from assistive automation to autonomous, goal-driven software agents. These agents can independently reason, plan, and execute complex verification tasks, such as generating code, creating testbenches, and analyzing gigabytes of error logs that previously required extensive manual engineering effort. This allows human engineers to focus on system architecture and innovation rather than routine tasks. Siemens' Questa One Agentic Toolkit is part of its broader Fuse EDA AI system and includes five distinct agents for tasks like RTL code generation, linting, and debugging. The system leverages large language models from NVIDIA, including Nemotron, to power its AI-driven workflows and integrates with common coding applications used by engineers. The impact of integrating AI into verification is significant, with early adopters reporting 28-35% reductions in verification cycle times and up to a 24% improvement in bug detection rates. Siemens itself has claimed that integrating AI into its EDA solutions can increase productivity by as much as ten times. This move is part of a larger arms race in the EDA industry, a market largely controlled by Siemens, Synopsys, and Cadence. All three are embedding AI and machine learning into their toolchains to manage the soaring complexity and cost of chip development, with Google also demonstrating that AI can reduce chip floorplanning from months to hours. The pressure to accelerate chip design is intensified by the rise of custom silicon projects from companies like Amazon, Google, and Meta for their own AI services. Last year, nearly 70% of projects in the application-specific integrated circuit (ASIC) market were delayed, highlighting the urgent need for AI-driven tools to automate repetitive tasks and shorten development timelines.