Siemens Deploys AI to Speed Up Chip Design
Siemens announced it is integrating agentic AI into its Questa One platform to accelerate the design and verification of integrated circuits. The company claims the AI-driven workflows will help engineers achieve faster and more trusted register-transfer level (RTL) sign-off for new chip designs.
The chip design industry is grappling with a massive verification gap, where the time and resources needed to check a chip's correctness are growing faster than the ability to design it. Modern System-on-Chip (SoC) designs can contain billions of transistors and mix digital, analog, and mixed-signal components, making traditional verification methods a significant bottleneck. Register-Transfer Level (RTL) sign-off is a critical pre-manufacturing milestone that verifies the chip's blueprint is structurally sound before it's physically created. Errors discovered after this stage can lead to costly and time-consuming "respins," where the entire manufacturing process has to be repeated. The "agentic AI" Siemens is deploying goes beyond simple automation; it involves AI systems that can set goals, reason, and orchestrate complex workflows across multiple tools. These AI agents function like a virtual design team, autonomously working on tasks like code generation, error checking, and debugging. Siemens' system leverages NVIDIA's NIM microservices and Nemotron models. The new Questa One Agentic Toolkit includes specific agents for generating code (RTL Code Agent), checking for design errors (Lint Agent), and analyzing failures (Debug Agent). This move is part of a larger industry race to integrate AI into Electronic Design Automation (EDA). Key competitors Synopsys and Cadence are also developing their own AI-driven platforms. In February 2026, Cadence announced its ChipStack AI Super Agent, also promising a 10x productivity increase in design and verification.
