Siemens Deploys Agentic AI for Chip Design Verification
Siemens announced it is using agentic AI in its Questa One solution to accelerate the design and verification of integrated circuits. The system uses AI-driven workflows combined with configurable human expertise to speed up the register-transfer level (RTL) sign-off process, a critical and complex step in chip development.
The shift to agentic AI in chip design is a direct response to a growing crisis in the semiconductor industry. As chips become exponentially more complex, the rate of first-silicon success has plummeted from 32% in 2020 to just 14% in 2024. This decline highlights a massive productivity gap, with verification consuming up to 70% of the total chip development cycle and a shortage of skilled engineers creating significant project delays. Siemens' Questa One Agentic Toolkit introduces a team of specialized AI agents designed to tackle this verification bottleneck. The toolkit includes five distinct agents: an RTL Code Agent for generating synthesizable code, a Lint Agent for checking design errors, a CDC Agent for clock domain crossing verification, a Verification Planning Agent for automating test plans, and a Debug Agent for analyzing failures. This multi-agent approach allows for a divide-and-conquer strategy to a highly complex problem. Unlike previous uses of AI that acted as copilots, these agentic systems function more like autonomous collaborators. They can independently reason, plan, and execute complex verification tasks that would typically require extensive human intervention. For example, the agents can work together to generate necessary collateral like testbenches and verification plans, execute simulations, and then analyze the results to identify and debug issues. A critical and notoriously difficult task these agents address is clock domain crossing (CDC) verification. Modern chips can have dozens or even thousands of asynchronous clock domains, and errors in how signals pass between them can lead to intermittent bugs that are nearly impossible to find and may require a costly full chip respin. The dedicated CDC Agent automates the detection of these potential hazards early in the design flow. Early adopters of the technology are reporting substantial improvements in efficiency. Akshay Aggarwal, a senior director of Engineering at MediaTek, stated that the productivity gains from the Questa One Agentic Toolkit were "both immediate and significant," with engineers becoming proficient within hours. In a more specific example of the time saved, another MediaTek manager noted that the system's generative AI capabilities saved "weeks of engineering time" on property assistance alone.
