TSMC SiPh push & 3nm squeeze
TSMC is moving its Compact Universal Photonic Engine (COUPE) silicon‑photonic packaging toward commercial production—work many vendors, reportedly including Apple, are tracking for high‑bandwidth AI interconnects. Meanwhile, TSMC says its 3nm capacity is fully booked through 2028, creating a sustained supply squeeze that could constrain future SoC feature roadmaps. (digitimes.com) (dataconomy.com) (benzinga.com)
TrendForce reports TSMC is targeting volume COUPE deployments in 2026 and uses its SoIC‑X die‑stacking to place an electrical die directly over a photonic die to minimize die‑to‑die impedance. (trendforce.com) Digitimes notes a TSMC vice‑president who co‑chairs the SEMI Silicon Photonics Industry Alliance has signaled a transition from lab work to commercial mass‑production plans for COUPE at recent industry events. (digitimes.com) TSMC COUPE implementations pair a photonic PIC built on ~65nm process geometry with a 6nm electronic integrated circuit (EIC) for control and DSP functions, according to technical writeups of TSMC materials. (pchardwarepro.com) TSMC‑presented benchmarks for COUPE‑style on‑package optics include target aggregate throughputs on the order of 12.8 Tbps for short‑reach interconnects used inside AI accelerators and switch modules. (tomshardware.com) Digitimes specifically lists Apple among vendors tracking COUPE for high‑bandwidth AI interconnects, and 3D InCites / IFTLE coverage shows TSMC planning COUPE integration into CoWoS/CPO packaging flows for data‑center modules. (digitimes.com) Industry reports say TSMC’s advanced‑node capacity — including N3 (3nm) — is effectively booked out through 2028 with major clients reserving slots for N2/2nm planning. (dataconomy.com) Independent analyst briefs show 3nm lead times stretching beyond ~50 weeks and CoWoS packaging demand outstripping supply by roughly 40–50%, while market analyses report some customers paying approximately 50–100% capacity premiums to secure scarce wafers. (siliconanalysts.com)
