Meta Taps AMD for Custom AI Accelerator Chip
An analysis details Meta AI's collaboration with AMD on a custom GPU designed for specific high-volume workloads. The chip utilizes a chiplet design and achieves over 95% software reuse from AMD's existing MI450 architecture, avoiding the cost of a full custom ASIC tapeout. This approach highlights how large tech firms are pursuing system-level hardware optimization for their AI infrastructure.
- This multi-year, multi-generation agreement will deploy up to 6 gigawatts of AMD Instinct GPUs to power Meta's AI infrastructure, with the first shipments beginning in the second half of 2026. The deal is valued at an estimated $60 billion to $100 billion over five years. - The collaboration extends beyond GPUs, making Meta a lead customer for AMD's 6th Gen EPYC CPUs, codenamed "Venice," and a future processor codenamed "Verano," which are optimized for AI workloads. - As part of the deal, AMD issued Meta a performance-based warrant to acquire up to 160 million shares of AMD stock. This structure, similar to a previous AMD deal with OpenAI, ties the equity compensation to specific GPU shipment milestones and AMD stock price targets. - The custom accelerator is based on AMD's MI450 architecture and is co-engineered through the Open Compute Project on the AMD Helios rack-scale platform, which was jointly developed with Meta for large-scale AI deployments. - This move is part of a broader industry trend of "big tech" companies like Google (TPU), Amazon (Trainium), and Microsoft (Maia) developing custom silicon to optimize for specific AI workloads, reduce costs, and decrease reliance on single suppliers like Nvidia. - Prior to this large-scale AMD partnership, Meta has been developing its own in-house chips, known as the Meta Training and Inference Accelerator (MTIA). The first generation, MTIA v1, was a 7nm chip focused on inference for recommendation models. - The chiplet design approach, used in both the custom Meta/AMD chip and AMD's broader MI300 series, allows for combining smaller, specialized dies into a single package. This improves manufacturing yield, lowers costs, and enables the integration of different functions and process nodes compared to a traditional monolithic chip.
